Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)
Latest Publications

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Published By IEEE

9781479913145, 9781479913121

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Detecting resistive-opens in RRAM using Programmable DfT scheme

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643558 ◽

2013 ◽

Author(s):

Nor Zaidi Haron ◽

Norsuhaidah Arshad ◽

Sukreen Hana Herman

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Simultaneous hotspot temperature and supply noise reductions using thermal TSVs and decoupling capacitors

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643595 ◽

2013 ◽

Author(s):

Yan-Wun Wang ◽

Pao-Jen Huang ◽

Tai-Chen Chen ◽

Chien-Nan Jimmy Liu

Keyword(s):

Decoupling Capacitors ◽

Supply Noise

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Mu-GSIM: A mutation testing simulator on GPUs

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643604 ◽

2013 ◽

Cited By ~ 1

Author(s):

Jason G. Tong ◽

Marc Boule ◽

Zeljko Zilic

Keyword(s):

Mutation Testing

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Innovative solutions for Package on Package test

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643580 ◽

2013 ◽

Author(s):

Chin Chien Tee ◽

Siang Soh

Keyword(s):

Innovative Solutions

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A new TSV set architecture for high reliability

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643574 ◽

2013 ◽

Cited By ~ 1

Author(s):

Jaeseok Park ◽

Sungho Kang

Keyword(s):

High Reliability

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Call for papers

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643551 ◽

2013 ◽

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Breakthrough of micro USB placement in printed circuit board

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643583 ◽

2013 ◽

Author(s):

Kent Lee ◽

Yow Huoy Thyng ◽

Oliver Hooi

Keyword(s):

Printed Circuit Board ◽

Circuit Board ◽

Printed Circuit

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[Back cover]

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643612 ◽

2013 ◽

Keyword(s):

Back Cover

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Path resistance reduction through automated Multi-Level Metal and Via insertion for IC layout design

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643597 ◽

2013 ◽

Author(s):

Thai Lee Lo ◽

Gregory Sylvester Emmanuel ◽

Thomas Fong Chee Goh ◽

Chun Keong Lee ◽

Joon Heong Ong ◽

...

Keyword(s):

Layout Design ◽

Resistance Reduction ◽

Multi Level

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Optimized clock gating cell for low power design in nanoscale CMOS technology

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013) ◽

10.1109/asqed.2013.6643569 ◽

2013 ◽

Cited By ~ 2

Author(s):

Aniryudh Reddy Durgam ◽

Ken Choi

Keyword(s):

Low Power ◽

Low Power Design ◽

Cmos Technology ◽

Clock Gating ◽

Nanoscale Cmos

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Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Detecting resistive-opens in RRAM using Programmable DfT scheme

Simultaneous hotspot temperature and supply noise reductions using thermal TSVs and decoupling capacitors

Mu-GSIM: A mutation testing simulator on GPUs

Innovative solutions for Package on Package test

A new TSV set architecture for high reliability

Call for papers

Breakthrough of micro USB placement in printed circuit board

[Back cover]

Path resistance reduction through automated Multi-Level Metal and Via insertion for IC layout design

Optimized clock gating cell for low power design in nanoscale CMOS technology

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)
Latest Publications