Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

A Comparative Analysis between Standard and mm-Wave Optimized BEOL in a Nanoscale CMOS Technology

This paper presents an extensive comparison of two 28-nm CMOS technologies, i.e., standard and mm-wave-optimized (i.e., thick metals and intermetal oxides) back-end-of-line (BEOL). The proposed comparison is carried out at both component and circuit level by means of a quantitative analysis of the actual performance improvements due to the adoption of a mm-wave-optimized BEOL. To this end, stand-alone transformer performance is first evaluated and then a complete mm-wave macroblock is investigated. A 77-GHz down-converter for frequency modulated continuous wave (FMCW) long-range/medium range (LR/MR) radar applications is exploited as a testbench. For the first time, it is demonstrated that thicker metals and intermetal oxides do not guarantee significant improvements at mm-wave frequencies and a standard (low-cost) BEOL is competitive in comparison with more complex (expensive) ones.

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.