13th International Symposium on the Physical and Failure Analysis of Integrated Circuits
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Published By IEEE

1424402050, 1424402069

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Lead frame Hillock-Induced Silicon Crack

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251040 ◽

2006 ◽

Author(s):

R.C. Flores ◽

M.G. Fabia ◽

M.T. Nabong ◽

A.O. Soria ◽

C.B. Gabunas

Keyword(s):

Lead Frame

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Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251045 ◽

2006 ◽

Cited By ~ 12

Author(s):

Junjun Li ◽

David Alvarez ◽

Kiran Chatty ◽

Michel Abou-khalil ◽

Robert Gauthier ◽

...

Keyword(s):

Failure Mechanism ◽

Cmos Technology

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Interface Characterization for Vertically Aligned Carbon Nanofibers for On-chip Interconnect Applications

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251048 ◽

2006 ◽

Author(s):

Yusuke Ominami ◽

Quoc Ngo ◽

Makoto Suzuki ◽

Kevin Mcilwrath ◽

Konrad Jarausch ◽

...

Keyword(s):

Carbon Nanofibers ◽

Interface Characterization ◽

Vertically Aligned ◽

Vertically Aligned Carbon Nanofibers ◽

On Chip

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Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251020 ◽

2006 ◽

Cited By ~ 1

Author(s):

Sergey Sofer ◽

Yefim Fefer ◽

Yoram Shapira

Keyword(s):

Electrostatic Discharge ◽

On Chip

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Reliability Improvement in Multi-level Cu/SiOC Low k Integration

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251009 ◽

2006 ◽

Cited By ~ 1

Author(s):

Y. W. Chen ◽

I.C. Chen ◽

Johnston Zou ◽

G. Zhang ◽

Steven Chen ◽

...

Keyword(s):

Reliability Improvement ◽

Multi Level ◽

Low K

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Low-k Dielectric Breakdown Improvement with Co(W,P) Cap Barrier

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251008 ◽

2006 ◽

Author(s):

Tam Tan ◽

Jesica ◽

Chee Gan ◽

Nam Hwang ◽

Jeffrey Gambino

Keyword(s):

Dielectric Breakdown ◽

Low K

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TEM application in the failure analysis of advanced 90 nm SOI-based IC devices

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251031 ◽

2006 ◽

Author(s):

K. Li ◽

E. Er ◽

S. Zhao

Keyword(s):

Failure Analysis

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Impact of the PCB design on the crack risk of CSP assemblies subjected to temperature cycling and drop tests

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251036 ◽

2006 ◽

Cited By ~ 2

Author(s):

H. Fremont ◽

M. Mura ◽

B. Plano ◽

W. Horaud ◽

Y. Danto

Keyword(s):

Temperature Cycling ◽

Pcb Design ◽

Drop Tests

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Tiny Pitts are the Yield Major Killer Caused by Metal Contamination in Wet Bench Cleaning

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251013 ◽

2006 ◽

Author(s):

Sheng-hsiung Chen ◽

Shen-li Chen ◽

Long-yeu Chung ◽

Wen-kuan Yeh

Keyword(s):

Metal Contamination

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The rules of the Rue Morgue: a decade later

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251000 ◽

2006 ◽

Cited By ~ 2

Author(s):

G. Mura ◽

M. Vanzi ◽

G. Cassanelli ◽

F. Fantini

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13th International Symposium on the Physical and Failure Analysis of Integrated CircuitsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Lead frame Hillock-Induced Silicon Crack

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

Interface Characterization for Vertically Aligned Carbon Nanofibers for On-chip Interconnect Applications

Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance

Reliability Improvement in Multi-level Cu/SiOC Low k Integration

Low-k Dielectric Breakdown Improvement with Co(W,P) Cap Barrier

TEM application in the failure analysis of advanced 90 nm SOI-based IC devices

Impact of the PCB design on the crack risk of CSP assemblies subjected to temperature cycling and drop tests

Tiny Pitts are the Yield Major Killer Caused by Metal Contamination in Wet Bench Cleaning

The rules of the Rue Morgue: a decade later

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits
Latest Publications