Improvement of inter layer dielectric crack for LQFP C90FG wafer technology devices in copper wire bonding process

Purpose This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process. Design/methodology/approach Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating. Findings Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack. Originality/value For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.

Optimasi Pergerakan Motor Stepper 3 Axis Dengan Metode Microstepping Dan Pembuatan Unique Code Pada Lead Frame

Perkembangan teknologi industri saat ini memang tidak bisa diragukan lagi semenjak munculnya industri 4.0 yang sangat menunjang produktifitas dan efektifitas. Hal ini semakin menuntut setiap perusahaan untuk lebih berkembang dan dapat bersaing dalam dunia industry. Oleh karena itu, dibutuhkan sistem yang dapat mengurangi pemakaian tenaga manusia tetapi tetap meningkatkan jumlah produktifitas. Microstepping merupakan sebuah mekanisme pada industri yang menggunakan fungsi dasar pada motor stepper yaitu pergerakan, dengan mengurangi probabilitas yang mungkin dapat menyebabkan timbulnya permasalahan pada sistem itu sendiri. Sistem ini diterapkan pada alat yang sebelumnya sudah dibuat bernama “Chip RFID Tester” yang berfungsi untuk melakukan pergerakan dalam pembacaan chip RFID yang tertera pada lead frame. Untuk peningkatan efisiensi yang mampu dilakukan oleh Chip RFID Tester dengan menggunakan metode microstepping mencapai ±50% dibandingkan dengan tidak menggunakan microstepping.

Modeling of Leadframe Strip Warpage after Die Attach Cure Process

In the leadframe package assembly process, silicon die is attached to the leadframe using a die attach adhesive material and the bonded strip is then cured. However, excessive strip warpage after the die attach cure process is a challenging problem that also affects the succeeding assembly processes. In this study, strip warpage modeling was done using a finite element analysis (FEA) technique to understand the warpage mechanism after die attach cure and find options to reduce strip warpage. The effect of changing the leadframe thickness, die thickness, and the leadframe design in terms of the number of strip panels or changing the connecting bar was analyzed. Modeling demonstrated that lead frame contracts faster than the silicon die resulting in the “frowning” warpage that agrees with the actual observation. It was also shown that increasing the die thickness by 25% results in 27% warpage reduction. Results also showed that increasing the number of panels or maps in a strip could significantly reduce the strip warpage. Improving the panel-to-panel isolation using stress relief cuts is also another option to reduce warpage after die attach cure.

Implementing Single-Row Process Plate Design for Pre-Encapsulated Lead Frame

This paper presents the application of an innovative design of wirebond process plate during wirebonding process of thin semiconductor carrier such as the pre-encapsulated leadframe. The implementation of the specialized process plate aims to improve the conventional method of wirebonding from panel type to single-row design to reduce the occurrence of warpage on thin leadframes. In this study, an 85% reduction for warpage level is achieved after the introduction of the new design of process plate. Future works could use the improved process plate design for devices of similar configuration.