2019 ◽  
Vol 28 (09) ◽  
pp. 1950142
Author(s):  
Linli Xu ◽  
Jing Han ◽  
Tian Wang ◽  
Lianfa Bai

In outdoor scenes, haze limits the visibility of images, and degrades people’s judgement of the objects. In this paper, based on an assumption of human visual perception in frequency domain, a novel image haze removal filtering is proposed. Combining this assumption with the theory of frequency domain filtering, we first estimate the cut-off frequency to divide the frequency domain of the hazy image into three components — low-frequency domain, intermediate-frequency domain and high-frequency domain. Then, by introducing the weighting factors, the three components are recombined together. After the theoretical deduction of frequency domain, the establishment of the actual model and adjusting the cut-off frequency and weighting factors, we finally acquire a global and adaptive filtering. This filtering can restore the details and the contours of the images, which have less noise, and improve the visibility of the objects in hazy images. Moreover, our method is simple in structure and strongly applicable, and rarely affected by parameters. Our algorithm is stable and performs well in heavy fog and the scene changes.


2018 ◽  
Vol 7 (2.16) ◽  
pp. 88 ◽  
Author(s):  
Latha Sahukar ◽  
Dr M. Madhavi Latha

This paper presents a sampling rate digital down converter that is totally based on frequency domain processing. The proposed DDC is targeted for Software Defined Radio and Cognitive Radio architectures. The proposed architecture is based on replacement of the complex multiplication with direct rotation of the spectrum. Different aspects of frequency domain filtering are also discussed. The Xilinx Virtex-6 family FPGA, XC6VLX240T is used for the implementation and synthesis of the proposed FFT-IFFT based architecture. The overlapping in time domain at the output of the IFFT block is avoided using overlap and add method. In terms area, highly optimized implementation is observed in the proposed architecture when compared to the conventional DDC. The synthesis results have shown that the developed core works at a maximum clock rate of 250 MHz and at the same time  occupies  only 10% of the slices of  FPGA. 


2014 ◽  
Vol 49 (6) ◽  
pp. 1303-1316 ◽  
Author(s):  
Amir Ghaffari ◽  
Eric A. M. Klumperink ◽  
Frank van Vliet ◽  
Bram Nauta

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