An Equalization Time Reduction Method Using a Pseudo-Random Number Sequence for a Cell Voltage Equalization Circuit with an LC Series Circuit

2016 ◽  
Vol 197 (3) ◽  
pp. 50-57 ◽  
Author(s):  
DAIKI SATOU ◽  
NOBUKAZU HOSHI
2013 ◽  
Vol 16 (2) ◽  
pp. 210-216 ◽  
Author(s):  
Sattar B. Sadkhan ◽  
◽  
Sawsan K. Thamer ◽  
Najwan A. Hassan ◽  
◽  
...  

Micromachines ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 31
Author(s):  
Junxiu Liu ◽  
Zhewei Liang ◽  
Yuling Luo ◽  
Lvchen Cao ◽  
Shunsheng Zhang ◽  
...  

Recent research showed that the chaotic maps are considered as alternative methods for generating pseudo-random numbers, and various approaches have been proposed for the corresponding hardware implementations. In this work, an efficient hardware pseudo-random number generator (PRNG) is proposed, where the one-dimensional logistic map is optimised by using the perturbation operation which effectively reduces the degradation of digital chaos. By employing stochastic computing, a hardware PRNG is designed with relatively low hardware utilisation. The proposed hardware PRNG is implemented by using a Field Programmable Gate Array device. Results show that the chaotic map achieves good security performance by using the perturbation operations and the generated pseudo-random numbers pass the TestU01 test and the NIST SP 800-22 test. Most importantly, it also saves 89% of hardware resources compared to conventional approaches.


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