UWB true-time-delay lines inspired by CRLH TL unit cells

2011 ◽  
Vol 53 (9) ◽  
pp. 1955-1961 ◽  
Author(s):  
J. Zhang ◽  
S.W. Cheung ◽  
T.I. Yuk
Author(s):  
Yakov Gutkin ◽  
Asher Madjar ◽  
Emanuel Cohen

Abstract In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.


2018 ◽  
Vol 36 (19) ◽  
pp. 4591-4601 ◽  
Author(s):  
Daniel Perez-Lopez ◽  
Erica Sanchez ◽  
Jose Capmany

1996 ◽  
Author(s):  
Wenshen Wang ◽  
Yongqiang Shi ◽  
Weiping Lin ◽  
James H. Bechtel

2015 ◽  
Vol 40 (4) ◽  
pp. 621 ◽  
Author(s):  
Sergi Garcia ◽  
Ivana Gasulla

1997 ◽  
Vol 9 (1) ◽  
pp. 100-102 ◽  
Author(s):  
R.L.Q. Li ◽  
R.T. Chen

2005 ◽  
Vol 17 (9) ◽  
pp. 1944-1946 ◽  
Author(s):  
B. Howley ◽  
Yihong Chen ◽  
Xiaolong Wang ◽  
Qingjun Zhou ◽  
Zhong Shi ◽  
...  

Author(s):  
Giorgio De Angelis ◽  
Andrea Lucibello ◽  
Romolo Marcelli ◽  
Simone Catoni ◽  
Antonio Lanciano ◽  
...  

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