A heterogeneous macro-model for power extraction of the Network-on-Chip router at system level is proposed, with higher accuracy to overcome the shortcoming of existing architecture-level power simulators, which is aimed to evaluate the network performance rapidly and guide the communication structure design. Each module of the router is modeled by different methods according to different characteristics. The input/output ports, the routing algorithm and the crossbar switch are established by multiple linear regression because of their single data flow state. The arbiter is established based on BP neural network due to its numerous states. Several experiments with different traffic loads and input sequences are carried out to verify the power model. Experimental results show that our power model is higher speed over the gate-level simulation, and the average estimation error is 5.0%. As a case study, we use the proposed model to evaluate the performance of different core mappings for H.264 decoder in system-level low power design.
Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip