Embedded e-maintenance for an FPGA-based reconfigurable system

In recent years with the use of Internet Technologies e-Maintenance systems for remote connectivity, performance monitoring and diagnostics were introduced. As reconfigurable system based on FPGAs are becoming more and more popular due to their low time-to-market and reprogrammable feature, new possibilities for e-Maintenance are opened allowing remote repair of the system by sending new firmware via Internet for reconfiguration of FPGA. Up until recently programming of FPGA has been a complicated hardware design process. However, as FPGAs were evolving, their reconfiguration time was significantly reduced and partial reconfiguration became available, application programming into FPGA can be simplified as presented in [1]. This method is based on temporal partitioning of FPGA and periodically reloading it with segments of application for different tasks. This allows utilization of smaller and thus much cheaper FPGA and also simplifies the programming. With the help of e-Maintenance the whole system can be dynamically reconfigured. Remote programmer can perform partial reconfiguration, close the physical location in FPGA for reconfiguration and upgrade different segments. In this project a research of remote maintenance and reconfigurable systems is conducted and e-Maintenance system is developed for an FPGA-based platform.

Embedded e-maintenance for an FPGA-based reconfigurable system

In recent years with the use of Internet Technologies e-Maintenance systems for remote connectivity, performance monitoring and diagnostics were introduced. As reconfigurable system based on FPGAs are becoming more and more popular due to their low time-to-market and reprogrammable feature, new possibilities for e-Maintenance are opened allowing remote repair of the system by sending new firmware via Internet for reconfiguration of FPGA. Up until recently programming of FPGA has been a complicated hardware design process. However, as FPGAs were evolving, their reconfiguration time was significantly reduced and partial reconfiguration became available, application programming into FPGA can be simplified as presented in [1]. This method is based on temporal partitioning of FPGA and periodically reloading it with segments of application for different tasks. This allows utilization of smaller and thus much cheaper FPGA and also simplifies the programming. With the help of e-Maintenance the whole system can be dynamically reconfigured. Remote programmer can perform partial reconfiguration, close the physical location in FPGA for reconfiguration and upgrade different segments. In this project a research of remote maintenance and reconfigurable systems is conducted and e-Maintenance system is developed for an FPGA-based platform.

On Predictable Reconfigurable System Design

We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.

Exterior Car Parking Assistance Algorithm Based on Reconfigurable System for Future Industry

A car accident while parking the car is caused by the car driver, who is invisible around the car. However, there are no solutions for parking assistance when the driver is outside the car. The objective of this paper is to propose a reconfigurable embedded system design by voice controlled parking assistance system for a prototype electric vehicle connected to a smartphone via Bluetooth. Hardware and software co-design using the Xilinx VIVADO as a software design tool is introduced. We design the hardware and software on an ARM multicore processor and the reconfigurable system board model ZYBO: XC7Z010 by considering it as hardware accelerator. The hardware of the proposed voice controlled exterior car parking assistance system is installed on the miniature electric vehicle. The experiments are tested successfully at the parking area for both reverse parking and reverse parallel parking. This proposed system is better suited for users so that they can control their car comfortably while parking safely.

Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-Chip

A heterogeneous system-on-chip (SoC) integrates multiple types of processors on the same chip. It has great advantages in many aspects, such as processing capacity, size, weight, cost, power, and energy consumption, which result in it being widely adopted in many fields. The SoC based on region-based dynamic partial reconfigurable (DPR) FPGA plays an important role in the SoC field. However, delivering its powerful capacity to the consumer depends on the efficient Sw/Hw partitioning and scheduling technology that determines the resource volume of the DPR region, the mapping of the application to the DPR region and other processors, and the schedule of the task and its reconfiguration. This paper first proposes an exact approach based on the mixed integer linear programming (MILP) for the Sw/Hw partitioning and scheduling problem. The proposed MILP is able to solve the problem optimally; however, its scalability is poor, despite that we carefully designed its formulation and tried to make it as concise as possible. Therefore, a multi-step hybrid method that combines graph partitioning and MILP is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. A set of experiments is carried out using a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.