scholarly journals Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm

Author(s):  
Henry Kuo ◽  
Ingrid Verbauwhede
Author(s):  
Badr Elkari ◽  
Hassan Ayad ◽  
Abdeljalil El Kari ◽  
Mostafa Mjahed

2009 ◽  
Vol 31 (3) ◽  
pp. 411-418
Author(s):  
Xin TIAN ◽  
Yi-Hua TAN ◽  
Jin-Wen TIAN

2004 ◽  
Vol 14 (01) ◽  
pp. 83-97
Author(s):  
JONG-CHUANG TSAY

A parenthesis string is a string of left and right parentheses. The string is well-formed when it consists of balanced pairs of left and right parentheses. This study presents a novel systolic algorithm for generating all the well-formed parenthesis strings in lexicographical order. The algorithm is cost-optimal and is run on a linear array of processors such that each well-formed parenthesis string can be generated in three time steps. The processor array is appropriate for VLSI implementation, since it has the features of modularity, regularity, and local connection.


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