decimation filter
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2021 ◽  
Vol 1208 (1) ◽  
pp. 012031
Author(s):  
Gordana Jovanovic Dolecek

Abstract This paper presents an efficient method to improve the comb aliasing rejection in a comb decimation filter without increasing its passband droop. This problem is important since aliasing and comb passband droop may deteriorate the decimated signal. We propose here to apply sharpening of the modified comb in the second stage of a two-stage comb structure. The modified comb is obtained by decreasing the middle coefficient of the impulse response of the cascade of two combs by 1/2. The sharpening polynomial with the first order tangencies is used here. As a result, the comb folding bands, where the aliasing occur, become wider and with an increased attenuation in comparison with the original comb filter. However, this improvement in the folding bands did not result in an increased passband droop. The compensator from literature is used to further decrease passband droop. The method is illustrated with examples and compared with the original comb and the methods proposed in literature for increasing aliasing rejection.


2021 ◽  
Author(s):  
Dongyu Li ◽  
Zhijie Chen ◽  
Xu Liu ◽  
Zhiqi Shen ◽  
Yanhui Xing ◽  
...  

Author(s):  
Tae-Woong Kang ◽  
Hyon-Ik Lee ◽  
Young-Bok Lee

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.


Author(s):  
V. R. Niveditha ◽  
Senthilnathan Palaniappan ◽  
K. Naresh ◽  
Chinmaya Kumar Nayak ◽  
B. Swapna

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