Logic Synthesis for Low Power

Logic Synthesis and Verification ◽

10.1007/978-1-4615-0817-5_8 ◽

2002 ◽

pp. 197-223 ◽

Cited By ~ 3

Author(s):

Luca Benini ◽

Giovanni Micheli

Keyword(s):

Low Power ◽

Logic Synthesis

Download Full-text

Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems ◽

10.1109/ddecs.2007.4295269 ◽

2007 ◽

Cited By ~ 2

Author(s):

I. Brzozowski ◽

A. Kos

Keyword(s):

Low Power ◽

Power Dissipation ◽

Logic Synthesis ◽

New Model

Download Full-text

Low power logic synthesis under a general delay model

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1145/280756.280900 ◽

1998 ◽

Cited By ~ 8

Author(s):

Unni Narayanan ◽

Peichen Pan ◽

C. L. Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Delay Model ◽

Low Power Logic

Download Full-text

Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness

9th International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2002.1046265 ◽

2003 ◽

Cited By ~ 6

Author(s):

T. Mahnke ◽

S. Panenka ◽

M. Embacher ◽

W. Stechele ◽

W. Hoeld

Keyword(s):

Low Power ◽

Supply Voltage ◽

Logic Synthesis ◽

Delay Constraint ◽

Varying Delay

Download Full-text

Low power logic synthesis under a general delay model

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1109/lpe.1998.708190 ◽

2002 ◽

Author(s):

U. Narayanan ◽

Peichen Pan ◽

C.L. Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Delay Model ◽

Low Power Logic

Download Full-text

Retiming-based logic synthesis for low-power

Proceedings of the International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.2002.146754 ◽

2002 ◽

Author(s):

Yu-Lung Hsu ◽

Sying-Jyan Wang

Keyword(s):

Low Power ◽

Logic Synthesis

Download Full-text