A 65 nm Duplex Transconductance Path Up-Conversion Mixer for 24 GHz Automotive Short-Range Radar Sensor Applications

A 24 GHz highly-linear upconversion mixer, based on a duplex transconductance path (DTP), is proposed for automotive short-range radar sensor applications using the 65-nm CMOS process. A mixer with an enhanced transconductance stage consisting of a DTP is presented to improve linearity. The main transconductance path (MTP) of the DTP includes a common source (CS) amplifier, while the secondary transconductance path (STP) of the DTP is implemented as an improved cross-quad transconductor (ICQT). Two inductors with a bypass capacitor are connected at the common nodes of the transconductance stage and switching stage of the mixer, which acts as a resonator and helps to improve the gain and isolation of the designed mixer. According to the measured results, at 24 GHz the proposed mixer shows that the linearity of output 1-dB compression point (OP1dB) is 3.9 dBm. And the input 1-dB compression point (IP1dB) is 0.9 dBm. Moreover, a maximum conversion gain (CG) of 2.49 dB and a noise figure (NF) of 3.9 dB is achieved in the designed mixer. When the supply voltage is 1.2 V, the power dissipation of the mixer is 3.24 mW. The mixer chip occupies an area of 0.42 mm2.

A CMOS Integrator-Based Clock-Free Time-to-Digital Converter for Home-Monitoring LiDAR Sensors

This paper presents a nine-bit integrator-based time-to-digital converter (I-TDC) realized in a 180 nm CMOS technology for the applications of indoor home-monitoring light detection and ranging (LiDAR) sensors. The proposed I-TDC exploits a clock-free configuration so as to discard clock-related dynamic power consumption and some notorious issues such as skew, glitch, and synchronization. It consists of a one-dimensional (1D) flash TDC to generate coarse-control codes and an integrator with a peak detection and hold (PDH) circuit to produce fine-control codes. A thermometer-to-binary converter is added to the 1D flash TDC, yielding four-bit coarse codes so that the measured detection range can be represented by nine-bit digital codes in total. Test chips of the proposed I-TDC demonstrate the measured results of the 53 dB dynamic range, i.e., the maximum detection range of 33.6 m and the minimum range of 7.5 cm. The chip core occupies the area of 0.14 × 1.4 mm2, with the power dissipation of 1.6 mW from a single 1.2-V supply.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Approximate Square Root Circuits with Low Latency and Power Dissipation

This paper proposes a series of approximate square root circuit designs with high accuracy, low latency, low area, and low power dissipation requirements. The proposed designs are constructed using an array of controlled add–subtract cell elements with both exact and approximate versions. The utility of the proposed designs are evaluated by utilizing them in an example image contrast enhancement application with demonstrably satisfactory results and large peak signal-to-noise ratios and structural similarity values. The accuracy and hardware characteristics of the proposed square root designs are also analyzed and compared with previously proposed state-of-the-art approximate square root designs. When applied to a 16-bit radicand (the number under the square root symbol), the proposed designs have the lowest error rates, normalized mean error distances, and mean relative error distances by at least 1.8x when compared to all previous methods using the same number of approximate cells. When the designs were synthesized using Synopsys Design Compiler with a 28 nm bulk CMOS process, the delay, area, power, and power-delay-product characteristics outperform all previous designs in all but a few cases. These results demonstrate that the proposed designs permit the use of a flexible range of approximate designs with varying accuracy and hardware overhead characteristics, and a suitable design can be selected based on the user design requirements.

Multi-directional Forging of Large-Scale Mg-9Gd-3Y-2Zn-0.5Zr Alloy Guided By 3D Processing Maps And Finite Element Analysis

The three-dimensional (3D) processing maps of cast Mg-9.0Gd-3.0Y-2.0Zn-0.5Zr alloy were established based on isothermal compression tests and dynamic material model (DMM). The stable and power efficient forming domains were determined by considering both the instability and power dissipation efficiency maps. Multi-directional forging (MDF) was then simulated by employing finite element (FE) analysis in the Deform-3D software, using the 3D power dissipation efficiency maps as input. The optimal forging parameters were thus obtained for a large-scale ingot with 430 mm in diameter and 440 mm in height, i.e. a forging temperature of 450 ℃ and forging speed of 10 mm/s. Finally, a Mg-9.0Gd-3.0Y-2.0Zn-0.5Zr cake-shaped forged part with 900 mm in diameter and 100 mm in height was produced. After T6-heat treatment, the edge and center of the forged part exhibit homogeneous microstructure and relatively consistent properties, with the tensile strength, yield strength and elongation being about 400 MPa, 320 MPa and 14.0% respectively. Using transmission electron microscopy, the main strengthening phases were revealed to be the dense nano-scale β' phases that are uniformly distributed inside the material.

Modeling and validation of nonlinear voltage-current characteristics of ITER PF joint sample tested in SULTAN facility

The ITER Poloidal Field (PF) coils are wound into double pancakes with NbTi cable-in-conduit conductors, which are connected by joints in shaking hands lap-type configuration. The coils are operating in pulsed mode with a maximum operating current of 55 kA and peak magnetic field of 6.4 T, utilizing electromagnetic load on the conductors and joints. A series of PF qualification joint samples modified in praying hands configuration is measured in the SULTAN facility. For some samples, a nonlinear voltage-current (VI) characteristic is observed during the assessment of joint resistance. The growth of joint resistance versus the B×I product is larger than what is expected from the magneto-resistant copper contribution. Two non-homogeneous contact resistance models are developed and combined to quantitatively evaluate the reason for the nonlinear VI behavior in combination with the relevant power dissipation and current redistribution in the joint. The simulations reveal that, for the particular pre-qualification PFJEU2 sample with resistance variation up to 3.5 nΩ, the most probable reason for the nonlinear VI characteristic is a widely spread defective connection between copper sole and shim. The electromagnetic force involves a separation effect on the mechanically and electrically weakly connected parts, resulting into a varying resistance depending on transport current and background field. The hypothesis and models are validated by an experiment on a similar sample PFJEU3 and a post-mortem examination of the PFJEU2 sample.

Location, Area, Curvature and Temporal Trends of Coral Sea Tropical Cyclone Tracks, Over 50 Years

Tropical Cyclones (TCs) with genesis in the Coral Sea, often near the east coast of Australia, present significant hazards to coastal regions in their surroundings. There has, therefore, been significant recent efforts to extract information from records of their historical tracks in order to help predict their future behaviour in the light of a changing climate. In this study, the Australian Bureau of Meteorology (BOM) database of TC tracks over the last fifty years were grouped based on K-means clustering of the maximum wind-weighted centroids. Track shape variance and track curvature (sinuosity) were assessed. Three well defined clusters of TC tracks were identified, and the results showed predominant directions of TC movement by cluster. Track sinuosity was shown to increase from east to west. Only one cluster showed a statistically significant trend (decreasing) in TC frequency. The concept of TC power dissipation index (PDI) was introduced, revealing that two of the clusters have diverging trends for PDI post 2004. The location of cyclone maximum intensity (LMI) was trended, and only one cluster showed a statistically significant trend (towards the equator) for LMI. All these findings demonstrated a clear variance in risk between the clusters and suggests that this method of cluster analysis is a useful and productive complementary tool when establishing future impacts of TCs - the method identifies divergent TC characteristics and trends at a finer scale (cluster) level which then aids in assigning specific and differing TC risk mitigation strategies to different areas of the Australian east coast.

Power optimization of binary division based on FPGA

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.