Chess : Retargetable Code Generation for Embedded DSP Processors

Code Generation for Embedded Processors ◽

10.1007/978-1-4615-2323-9_5 ◽

2002 ◽

pp. 85-102 ◽

Author(s):

Dirk Lanneer ◽

Johan Praet ◽

Augusli Kifli ◽

Koen Schoofs ◽

Werner Geurts ◽

...

Keyword(s):

Code Generation ◽

Embedded Dsp ◽

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Code density optimization for embedded DSP processors using data compression techniques

Proceedings Sixteenth Conference on Advanced Research in VLSI ◽

10.1109/arvlsi.1995.515626 ◽

2002 ◽

Author(s):

S.Y. Liao ◽

S. Devadas ◽

K. Keutzer

Keyword(s):

Data Compression ◽

Embedded Dsp ◽

Dsp Processors ◽

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An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1109/lpe.1998.708172 ◽

2002 ◽

Author(s):

C.H. Gebotys ◽

R.J. Gebotysu

Keyword(s):

High Performance ◽

Prediction Models ◽

Empirical Comparison ◽

Power Prediction ◽

Embedded Dsp ◽

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Statistically based prediction of power dissipation for complex embedded DSP processors

Microprocessors and Microsystems ◽

10.1016/s0141-9331(99)00030-7 ◽

1999 ◽

Vol 23 (3) ◽

pp. 135-144 ◽

Author(s):

C.H Gebotys ◽

R.J Gebotys

Keyword(s):

Power Dissipation ◽

Embedded Dsp ◽

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Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/315773.315776 ◽

1999 ◽

Vol 4 (3) ◽

pp. 231-256 ◽

Author(s):

Wei-Kai Cheng ◽

Youn-Long Lin

Keyword(s):

Code Generation ◽

Nested Loops ◽

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Simulated evolution based code generation for programmable DSP processors

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97 ◽

10.1109/iscas.1997.612855 ◽

2002 ◽

Author(s):

Yin-Tsung Hwang ◽

Jer-Sho Hwang

Keyword(s):

Code Generation ◽

Simulated Evolution ◽

Dsp Processors ◽

Programmable Dsp

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An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1145/280756.280824 ◽

1998 ◽

Author(s):

Catherine H. Gebotys ◽

Robert J. Gebotys

Keyword(s):

High Performance ◽

Prediction Models ◽

Empirical Comparison ◽

Power Prediction ◽

Embedded Dsp ◽

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Code density optimization for embedded DSP processors using data compression techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.709398 ◽

1998 ◽

Vol 17 (7) ◽

pp. 601-608 ◽

Author(s):

S.Y. Liao ◽

S. Devadas ◽

K. Keutzer

Keyword(s):

Data Compression ◽

Embedded Dsp ◽

Dsp Processors ◽

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Address code generation utilizing memory sharing in DSP processors

48th Midwest Symposium on Circuits and Systems, 2005. ◽

10.1109/mwscas.2005.1594167 ◽

2005 ◽

Author(s):

Taewhan Kim ◽

Shin Hong

Keyword(s):

Code Generation ◽

Memory Sharing ◽

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ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e98.a.2494 ◽

2015 ◽

Vol E98.A (12) ◽

pp. 2494-2504 ◽

Author(s):

Masashi TAWADA ◽

Shinji KIMURA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

Code Generation ◽

Non Volatile Memory ◽

Volatile Memory

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Privacy Concern Code Generation Using Crypto Neural Scheme

International Journal of Computer Sciences and Engineering ◽

10.26438/ijcse/v7i5.824828 ◽

2019 ◽

Vol 7 (5) ◽

pp. 824-828

Author(s):

Anaswara Venunadh ◽

Shruthi N ◽

Mannar Mannan

Keyword(s):

Code Generation ◽

Privacy Concern

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