Address code generation utilizing memory sharing in DSP processors

Author(s):  
Taewhan Kim ◽  
Shin Hong
Author(s):  
Dirk Lanneer ◽  
Johan Praet ◽  
Augusli Kifli ◽  
Koen Schoofs ◽  
Werner Geurts ◽  
...  

Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA

2019 ◽  
Vol 7 (5) ◽  
pp. 824-828
Author(s):  
Anaswara Venunadh ◽  
Shruthi N ◽  
Mannar Mannan

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3635 ◽  
Author(s):  
Guoming Zhang ◽  
Xiaoyu Ji ◽  
Yanjie Li ◽  
Wenyuan Xu

As a critical component in the smart grid, the Distribution Terminal Unit (DTU) dynamically adjusts the running status of the entire smart grid based on the collected electrical parameters to ensure the safe and stable operation of the smart grid. However, as a real-time embedded device, DTU has not only resource constraints but also specific requirements on real-time performance, thus, the traditional anomaly detection method cannot be deployed. To detect the tamper of the program running on DTU, we proposed a power-based non-intrusive condition monitoring method that collects and analyzes the power consumption of DTU using power sensors and machine learning (ML) techniques, the feasibility of this approach is that the power consumption is closely related to the executing code in CPUs, that is when the execution code is tampered with, the power consumption changes accordingly. To validate this idea, we set up a testbed based on DTU and simulated four types of imperceptible attacks that change the code running in ARM and DSP processors, respectively. We generate representative features and select lightweight ML algorithms to detect these attacks. We finally implemented the detection system on the windows and ubuntu platform and validated its effectiveness. The results show that the detection accuracy is up to 99.98% in a non-intrusive and lightweight way.


2014 ◽  
Vol 1008-1009 ◽  
pp. 659-662
Author(s):  
Hai Ke Liu ◽  
Shun Wang ◽  
Xin Gna Kang ◽  
Jin Liang Wang

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.


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