Design Methodology of Topological Structure of Interconnection Networks

2001 ◽  
pp. 39-104
Author(s):  
Junming Xu
Keyword(s):  
Topological Structure ◽  
Interconnection Networks ◽  
Design Methodology

DEVELOPMENT OF MAGNETIC GEAR MECHANISMS

2017 ◽  
Vol 41 (5) ◽  
pp. 758-770
Author(s):  
Yi-Chang Wu ◽  
Chin-Tsung Chan
Keyword(s):  
Mechanism Design ◽  
Topological Structure ◽  
Design Methodology ◽  
Permanent Magnets ◽  
Graph Representation ◽  
Speed Ratio ◽  
Design Requirements ◽  
Magnetic Gear ◽  
Novel Design ◽  
The Magnetic Field

The purpose of this study is to develop novel magnetic gear mechanisms by using creative mechanism design methodology. First, the flowchart of creative mechanism design methodology is introduced. The schematic diagram and graph representation of a magnetic gear device based on its topological structure are presented. Next, the characteristics of the topological structure of an existing 4-link magnetic gear device are analyzed. Feasible specialized chains are then enumerated, subject to design requirements and constraints. The direction of magnetization in permanent magnets is defined and applied to magnetic gear mechanisms. Finally, 12 novel magnetic gear mechanisms with 5 links are synthesized. The magnetic field, transmitted torque and speed ratio of a novel design are analyzed by 2-D FEA.

A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture

2011 ◽  
pp. 209-234
Author(s):  
Y. Aydi ◽  
M. Baklouti ◽  
Ph. Marquet ◽  
M. Abid ◽  
J.L. Dekeyser
Keyword(s):  
Communication Networks ◽  
Interconnection Networks ◽  
Design Methodology ◽  
Parallel Systems ◽  
Parallel Applications ◽  
Multistage Interconnection Networks ◽  
Networks On Chip ◽  
Data Intensive ◽  
Cost Metrics ◽  
On Chip

Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage networks on chip dedicated to parallel multi-cores architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through data parallel applications with different number of cores. We also show in the proposed framework that multistage interconnection networks are cost-effective high performance networks for parallel SOCs.

scholarly journals De-coding the possibilities of spatial asssemblages: a design methodology of topologizing architectural morphology

2020 ◽  
Vol 13 (2) ◽  
pp. 169-184
Author(s):  
Yota Passia ◽  
Panagiotis Roupas
Keyword(s):  
Continuous Flow ◽  
Topological Structure ◽  
Design Patterns ◽  
Design Methodology ◽  
Design Space ◽  
Structure Design ◽  
Material Reality ◽  
Productive Process ◽  
The City ◽  
Generative System

While the continuous flow of events seems to be a given, we still cannot either perceive or design space which is organized and has the capacity to reorganize itself in order to cope with major changes. In this framework, the research aims to establish a codefor space, as a semantic system that monitors its sociospatial metabolism while at the same time being directly connected to its material reality. In this framework, the research attempts to establish a design methodologyaiming at a generative system for architecture and the city. The material agency of this productive process is described as a bifold process which constantly informs itself, including a "convergent phase of selection"and a "divergent phase of design" (Spuybroek 2008: 189). The first one focuses on the code's organization, introducing Christopher Alexander's 253 Design Patterns (Alexander et al. 1977) as its elementary units in order to postulate on its topological structure as a network of relations between interacting, active parts. In the next phase, while theorizing the code's structure, Design Patterns are substituted by their A-signifying signs counterparts, mechanisms able to stabilize or destabilize the assemblage and thus allow for its contingency to remain immanent.

scholarly journals Computing Eccentricity-Based Topological Indices of 2-Power Interconnection Networks

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Muhammad Imran ◽  
Muhammad Azhar Iqbal ◽  
Yun Liu ◽  
Abdul Qudair Baig ◽  
Waqas Khalid ◽  
...  
Keyword(s):  
Topological Structure ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Topological Indices ◽  
Connectivity Index ◽  
Eccentric Connectivity Index ◽  
Zagreb Index ◽  
Eccentricity Index ◽  
Computer Scientists ◽  
Partition Method

In a connected graph G with a vertex v, the eccentricity εv of v is the distance between v and a vertex farthest from v in the graph G. Among eccentricity-based topological indices, the eccentric connectivity index, the total eccentricity index, and the Zagreb index are of vital importance. The eccentric connectivity index of G is defined by ξG = ∑v∈VGdvεv, where dv is the degree of the vertex v and εv is the eccentricity of v in G. The topological structure of an interconnected network can be modeled by using graph explanation as a tool. This fact has been universally accepted and used by computer scientists and engineers. More than that, practically, it has been shown that graph theory is a very powerful tool for designing and analyzing the topological structure of interconnection networks. The topological properties of the interconnection network have been computed by Hayat and Imran (2014), Haynes et al. (2002), and Imran et al. (2015). In this paper, we compute the close results for eccentricity-based topological indices such as the eccentric connectivity index, the total eccentricity index, and the first, second, and third Zagreb eccentricity index of a hypertree, sibling tree, and X-tree for k-level by using the edge partition method.

Longest Cycles Embedding in Faulty Augmented Cube Networks

2010 ◽  
Vol 159 ◽  
pp. 285-290
Author(s):  
Hong Mei Liu ◽  
Yan Juan Zhang ◽  
Yi Han Fan
Keyword(s):  
Parallel Computation ◽  
Topological Structure ◽  
Interconnection Networks ◽  
Longest Cycles ◽  
Augmented Cube

The augmented cube is one of the most versatile and efficient interconnection networks (networks for short) so far discovered for parallel computation. In this paper, the topological structure of dimensional augmented cube is analyzed. The properties related to cycle embedding in faulty have been investigated. Let denote the set of fault links. This study demonstrates that when , for each nonfault link of augmented cube networks, lies on a longest fault free cycle which contains every nodes of .

Review of Heuristic research: Design, methodology, and applications.

1991 ◽  
Vol 19 (2) ◽  
pp. 237-238
Author(s):  
Christopher M. Aanstoos
Keyword(s):  
Research Design ◽  
Design Methodology ◽  
Heuristic Research
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