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Semiconductor memory architecture
Testing Static Random Access Memories - Frontiers in Electronic Testing
◽
10.1007/978-1-4757-6706-3_2
◽
2004
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pp. 17-35
Author(s):
Said Hamdioui
Keyword(s):
Memory Architecture
◽
Semiconductor Memory
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Semiconductor Memory Architecture
Digital Electronic Circuits
◽
10.1142/9789813270732_0005
◽
2018
◽
pp. 215-247
Keyword(s):
Memory Architecture
◽
Semiconductor Memory
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Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules
Proceedings of the International Symposium on Memory Systems - MEMSYS '19
◽
10.1145/3357526.3357541
◽
2019
◽
Cited By ~ 4
Author(s):
Onkar Patil
◽
Latchesar Ionkov
◽
Jason Lee
◽
Frank Mueller
◽
Michael Lang
Keyword(s):
Memory Architecture
◽
Performance Characterization
◽
Hybrid Memory
◽
Persistent Memory
◽
Memory Modules
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Technological Design of 3D NAND based Compute-in-Memory Architecture for GB-scale Deep Neural Network
IEEE Electron Device Letters
◽
10.1109/led.2020.3048101
◽
2020
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pp. 1-1
Author(s):
Wonbo Shim
◽
Shimeng Yu
Keyword(s):
Neural Network
◽
Deep Neural Network
◽
Memory Architecture
◽
Technological Design
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A main frame semiconductor memory for fourth generation computers
10.1145/1478559.1478616
◽
1969
◽
Cited By ~ 2
Author(s):
Thomas W. Hart
◽
Durrell W. Hillis
◽
John Marley
◽
Robert C. Lutz
◽
Charles R. Hoffman
Keyword(s):
Fourth Generation
◽
Semiconductor Memory
◽
Main Frame
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TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries
Proceedings of the 2020 on Great Lakes Symposium on VLSI
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10.1145/3386263.3406896
◽
2020
◽
Author(s):
Sheng Xu
◽
Xiaoming Chen
◽
Xuehai Qian
◽
Yinhe Han
Keyword(s):
Memory Architecture
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CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
◽
10.1109/micro50266.2020.00038
◽
2020
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Author(s):
Dibei Chen
◽
Zhaoshi Li
◽
Tianzhu Xiong
◽
Zhiwei Liu
◽
Jun Yang
◽
...
Keyword(s):
Constant Time
◽
Memory Architecture
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Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics
2020 57th ACM/IEEE Design Automation Conference (DAC)
◽
10.1109/dac18072.2020.9218624
◽
2020
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Author(s):
Abraham Addisie
◽
Valeria Bertacco
Keyword(s):
Memory Architecture
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Graph Analytics
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MANNA: prototype of a distributed memory architecture with maximized sustained performance
Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing
◽
10.1109/empdp.1996.500600
◽
2002
◽
Cited By ~ 8
Author(s):
W.K. Giloi
◽
U. Bruening
◽
W. Schroeder-Preikschat
Keyword(s):
Distributed Memory
◽
Memory Architecture
◽
Sustained Performance
◽
Distributed Memory Architecture
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4401904 Delay circuit used in semiconductor memory device
Microelectronics Reliability
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10.1016/0026-2714(84)90868-0
◽
1984
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Vol 24
(1)
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pp. 195
Author(s):
LionelS White
◽
NgaiH Hong
Keyword(s):
Memory Device
◽
Semiconductor Memory
◽
Delay Circuit
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Parallelization Strategy for Elementary Morphological Operators on Graphs: Distance-Based Algorithms and Implementation on Multicore Shared-Memory Architecture
Journal of Mathematical Imaging and Vision
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10.1007/s10851-017-0737-1
◽
2017
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Vol 59
(1)
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pp. 136-160
◽
Cited By ~ 2
Author(s):
Imane Youkana
◽
Jean Cousty
◽
Rachida Saouli
◽
Mohamed Akil
Keyword(s):
Shared Memory
◽
Memory Architecture
◽
Morphological Operators
◽
Parallelization Strategy
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