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Probabilistic Verification for Reliable Network-on-Chip System Design
Formal Methods for Industrial Critical Systems - Lecture Notes in Computer Science
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10.1007/978-3-030-27008-7_7
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2019
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pp. 110-126
Author(s):
Benjamin Lewis
◽
Arnd Hartmanns
◽
Prabal Basu
◽
Rajesh Jayashankara Shridevi
◽
Koushik Chakraborty
◽
...
Keyword(s):
System Design
◽
Network On Chip
◽
Probabilistic Verification
◽
On Chip
Download Full-text
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References
Algorithms and tools for network on chip based system design
16th Symposium on Integrated Circuits and Systems Design 2003 SBCCI 2003 Proceedings SBCCI-03
◽
10.1109/sbcci.2003.1232823
◽
2004
◽
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Tang Lei
◽
S. Kumar
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System Design
◽
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Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System
10.1007/978-3-030-85248-1_16
◽
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◽
pp. 232-248
Author(s):
Riley Roberts
◽
Benjamin Lewis
◽
Arnd Hartmanns
◽
Prabal Basu
◽
Sanghamitra Roy
◽
...
Keyword(s):
Network On Chip
◽
Probabilistic Verification
◽
On Chip
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Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design
IEEE Transactions on Computers
◽
10.1109/tc.2017.2770130
◽
2018
◽
Vol 67
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◽
pp. 528-542
◽
Cited By ~ 12
Author(s):
Kanchan Manna
◽
Priyajit Mukherjee
◽
Santanu Chattopadhyay
◽
Indranil Sengupta
Keyword(s):
System Design
◽
Network On Chip
◽
Application Mapping
◽
Mapping Strategy
◽
On Chip
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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders
Oct. 17-19, 2017 Dubai (UAE)
◽
10.15242/dirpub.dir1017020
◽
2018
◽
Keyword(s):
Real Time
◽
Network On Chip
◽
On Chip
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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs
Artificial Intelligence and Industrial Application
◽
10.2495/aiia140551
◽
2015
◽
Author(s):
J. Fang
◽
L. Yu
◽
Z. Y. Leng
Keyword(s):
Routing Algorithm
◽
Network On Chip
◽
Tree Architecture
◽
On Chip
◽
Congestion Aware
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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications
i-manager’s Journal on Electronics Engineering
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10.26634/jele.5.1.3320
◽
2014
◽
Vol 5
(1)
◽
pp. 27-32
Author(s):
Jeeva Anusha
◽
◽
V. Thrimurthulu
◽
Keyword(s):
Vlsi Design
◽
Network On Chip
◽
Energy Modeling
◽
Low Energy
◽
On Chip
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Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip
JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY
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10.3724/sp.j.1146.2012.00654
◽
2014
◽
Vol 35
(2)
◽
pp. 341-346
Author(s):
Xiao-fu Zheng
◽
Hua-xi Gu
◽
Yin-tang Yang
◽
Zhong-fan Huang
Keyword(s):
Network On Chip
◽
Low Latency
◽
Router Architecture
◽
On Chip
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Example Antenna and Link Performance for Wireless Network on Chip Applications
12th European Conference on Antennas and Propagation (EuCAP 2018)
◽
10.1049/cp.2018.0956
◽
2018
◽
Author(s):
W. Rayess
◽
D.W. Matolak
Keyword(s):
Wireless Network
◽
Network On Chip
◽
Link Performance
◽
On Chip
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An optimized path-setup method for mesh based Optical Network on Chip
2015 14th International Conference on Optical Communications and Networks (ICOCN)
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10.1109/icocn.2015.7203619
◽
2015
◽
Author(s):
Wei Tan
◽
Bowen Zhang
◽
Huaxi Gu
◽
Zheng Chen
Keyword(s):
Optical Network
◽
Network On Chip
◽
On Chip
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A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes
2020 International SoC Design Conference (ISOCC)
◽
10.1109/isocc50952.2020.9332940
◽
2020
◽
Author(s):
Jiayi Liu
◽
Kejie Huang
Keyword(s):
Network On Chip
◽
Convolutional Networks
◽
On Chip
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