Automatic Generation of Guard-Stable Floating-Point Code

2020 ◽  
pp. 141-159
Author(s):  
Laura Titolo ◽  
Mariano Moscato ◽  
Marco A. Feliu ◽  
César A. Muñoz
Keyword(s):  
Automatic Generation ◽  
Floating Point ◽  
Point Code

scholarly journals Symbolic Crosschecking of Data-Parallel Floating-Point Code

2014 ◽  
Vol 40 (7) ◽  
pp. 710-737 ◽  
Author(s):  
Peter Collingbourne ◽  
Cristian Cadar ◽  
Paul H.J. Kelly
Keyword(s):  
Floating Point ◽  
Data Parallel ◽  
Point Code

scholarly journals Achieving high coverage for floating-point code via unconstrained programming

2017 ◽  
Vol 52 (6) ◽  
pp. 306-319 ◽  
Author(s):  
Zhoulai Fu ◽  
Zhendong Su
Keyword(s):  
Floating Point ◽  
High Coverage ◽  
Point Code

Automatic Generation of Floating-Point Test Data

1976 ◽  
Vol SE-2 (3) ◽  
pp. 223-226 ◽  
Author(s):  
W. Miller ◽  
D.L. Spooner
Keyword(s):  
Test Data ◽  
Automatic Generation ◽  
Floating Point ◽  
Point Test

The Role of Visual Distractors in the Simon Effect

2017 ◽  
Vol 64 (6) ◽  
pp. 387-397 ◽  
Author(s):  
Luisa Lugli ◽  
Stefania D’Ascenzo ◽  
Roberto Nicoletti ◽  
Carlo Umiltà
Keyword(s):  
Simon Effect ◽  
Simon Task ◽  
Automatic Generation ◽  
Spatial Code ◽  
Attentional Model ◽  
Previous Evidence ◽  
Spatial Stimulus ◽  
Attentional Resources ◽  
Code Changes

Abstract. The Simon effect lies on the automatic generation of a stimulus spatial code, which, however, is not relevant for performing the task. Results typically show faster performance when stimulus and response locations correspond, rather than when they do not. Considering reaction time distributions, two types of Simon effect have been individuated, which are thought to depend on different mechanisms: visuomotor activation versus cognitive translation of spatial codes. The present study aimed to investigate whether the presence of a distractor, which affects the allocation of attentional resources and, thus, the time needed to generate the spatial code, changes the nature of the Simon effect. In four experiments, we manipulated the presence and the characteristics of the distractor. Findings extend previous evidence regarding the distinction between visuomotor activation and cognitive translation of spatial stimulus codes in a Simon task. They are discussed with reference to the attentional model of the Simon effect.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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