A Configurable Hardware Architecture for Runtime Application of Network Calculus

2021 ◽  
pp. 203-216
Author(s):  
Xiao Hu ◽  
Zhonghai Lu
Keyword(s):  
Hardware Architecture ◽  
Network Calculus ◽  
Configurable Hardware

scholarly journals An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking

VLSI Design ◽  
2000 ◽  
Vol 10 (3) ◽  
pp. 249-263
Author(s):  
Zhen Luo ◽  
Margaret Martonosi ◽  
Pranav Ashar
Keyword(s):  
Layout Design ◽  
Hardware Architecture ◽  
Design Rule ◽  
Hardware Accelerators ◽  
Clock Rate ◽  
Design Rules ◽  
Vlsi Layout ◽  
Rule Checking ◽  
Design Rule Checking ◽  
Configurable Hardware

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking and a general scalable architecture for DRC. We then demonstrate our approach by applying this architecture to a set of design rules for MOSIS SCN4N_SUB process. We have implemented several design rule checks within a single Xilinx XC4013 FPGA and demonstrated overall speedups in excess of 25X over software methods. We have used a Compaq Pamette board to do the hardware prototyping and have achieved a clock rate of 33 MHz.

A New Hardware Architecture for Fuzzy Logic System Acceleration

2016 ◽  
Vol 12 (2) ◽  
pp. 188-197
Author(s):  
A yahoo.com ◽  
Aumalhuda Gani Abood aumalhuda ◽  
A comp ◽  
Dr. Mohammed A. Jodha ◽  
Dr. Majid A. Alwan
Keyword(s):  
Fuzzy Logic ◽  
Fuzzy Logic System ◽  
Hardware Architecture ◽  
Logic System
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