Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking
(DRC) were hobbled by the fact that it is often impractical to build a different rulechecking
ASIC each time design rules or fabrication processes change. In this paper, we
propose a configurable hardware approach to DRC. It can garner impressive speedups
over software approaches, while retaining the flexibility needed to change the rule checker
as rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattan
geometry checking and a general scalable architecture for DRC. We then demonstrate
our approach by applying this architecture to a set of design rules for MOSIS
SCN4N_SUB process. We have implemented several design rule checks within a single
Xilinx XC4013 FPGA and demonstrated overall speedups in excess of 25X over software
methods. We have used a Compaq Pamette board to do the hardware prototyping and
have achieved a clock rate of 33 MHz.
An Edge-endpoint-based Configurable Hardware
Architecture for VLSI Layout Design Rule Checking