A Hybrid Approach for Parallel Transistor-Level Full-Chip Circuit Simulation
1994 ◽
Vol 141
(4)
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pp. 241
Keyword(s):
2014 ◽
Vol 134
(4)
◽
pp. 173-181
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2011 ◽
Vol 131
(12)
◽
pp. 1024-1030
2010 ◽
Vol 130
(5)
◽
pp. 416-422
Keyword(s):
2011 ◽
Vol 131
(11)
◽
pp. 1309-1315
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