scholarly journals Optimal Tiling Strategy for Memory Bandwidth Reduction for CNNs

2017 ◽  
pp. 89-100 ◽  
Author(s):  
Leonardo Cecconi ◽  
Sander Smets ◽  
Luca Benini ◽  
Marian Verhelst
Keyword(s):  
Memory Bandwidth ◽  
Bandwidth Reduction

A High Performance Hardware Architecture of Sub-Pixel Interpolator for H.264/AVC Encoder

2012 ◽  
Vol 479-481 ◽  
pp. 2521-2524
Author(s):  
Guang Hua Chen ◽  
Wen Peng Su ◽  
Feng Jiao Wang ◽  
An Qi Wang ◽  
Wei Min Zeng ◽  
...  
Keyword(s):  
Real Time ◽  
High Performance ◽  
Block Size ◽  
Hardware Architecture ◽  
Data Reuse ◽  
Memory Bandwidth ◽  
Bandwidth Reduction ◽  
Variable Block ◽  
One Step ◽  
Processing Cycle

The design of H.264/AVC interpolation unit is very challenging for the high memory bandwidth and large calculation complexity caused by the new coding features of variable block size (VBS) and 6-tap filter. In this paper, a novel one-step interpolation implementation algorithm is proposed which can effectively reduce processing cycle because of its less memory accessing. Moreover, a data reuse scheme is used to save processing cycle and memory bandwidth. A high performance hardware architecture is implemented according to the methods mentioned above. As a result, 26% memory bandwidth reduction and 45% processing cycle reduction are achieved, which shows that our architecture is an efficient hardware accelerating solution and can be used in real-time encoder.

scholarly journals Memory bandwidth reduction using frame pipeline in video codec chips

2014 ◽  
Vol 11 (15) ◽  
pp. 20140592-20140592
Author(s):  
Yun Gu Lee ◽  
Ki-Hoon Lee ◽  
Woosaeng Kim
Keyword(s):  
Video Codec ◽  
Memory Bandwidth ◽  
Bandwidth Reduction
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