A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits

2008 ◽  
pp. 47-58 ◽  
Author(s):  
Zhifang Li ◽  
Wenjian Luo ◽  
Xufa Wang
Keyword(s):  
Dimension Reduction ◽  
Logic Circuits ◽  
Evolutionary Design ◽  
Combinational Logic ◽  
Combinational Logic Circuits ◽  
Reduction Approach

scholarly journals Evolutionary Design of Combinational Logic Circuits

2004 ◽  
Vol 8 (5) ◽  
pp. 507-513 ◽  
Author(s):  
Cecília Reis ◽  
◽  
J. A. Tenreiro Machado ◽  
J. Boaventura Cunha ◽  
Keyword(s):  
Genetic Algorithm ◽  
Full Adder ◽  
Logic Circuits ◽  
Evolutionary Design ◽  
Combinational Logic ◽  
Case Examples ◽  
Parity Checker ◽  
Minimum Number ◽  
Combinational Logic Circuits

This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.

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