Switch-level dynamic fault modeling for resistive short and open faults in nanometre technologies

Modeling the dynamic behaviour of resistive shorts and opens at switch-level dictates the characterization o enhanced delay attributable to these faults with referenc to the input combinations, fault sites, defect resistance and CMOS technology variation. Resistive physical failures make the output voltage fluctuate between intermediate ranges by disturbing the propagation time of the logic, without adversely changing the functional output. To determine the impact of logic propagation delay (tp) on the output voltage (Vout) of a gate, a switch-level fault analysis on CMOS primitive gates is executed for CMOS technologies 350 nm, 180 nm, and 90 nm in comparison with nanometre technologies 45 nm and 32 nm. To understand the nature and effect of actual resistive faults in silicon, static faults in static primitive gates are reviewed after altering the defect resistance. Delay and output voltage changes induced by these variations are determined for CMOS 32 nm technology.

Switch-level dynamic fault modeling for resistive short and open faults in nanometre technologies

Modeling the dynamic behaviour of resistive shorts and opens at switch-level dictates the characterization o enhanced delay attributable to these faults with referenc to the input combinations, fault sites, defect resistance and CMOS technology variation. Resistive physical failures make the output voltage fluctuate between intermediate ranges by disturbing the propagation time of the logic, without adversely changing the functional output. To determine the impact of logic propagation delay (tp) on the output voltage (Vout) of a gate, a switch-level fault analysis on CMOS primitive gates is executed for CMOS technologies 350 nm, 180 nm, and 90 nm in comparison with nanometre technologies 45 nm and 32 nm. To understand the nature and effect of actual resistive faults in silicon, static faults in static primitive gates are reviewed after altering the defect resistance. Delay and output voltage changes induced by these variations are determined for CMOS 32 nm technology.

A Method for Diagnosing Soft Short and Open Faults in Distributed Parameter Multiconductor Transmission Lines

This paper aims to develop a method for diagnosing soft short and open faults occurring in a distributed parameter multiconductor transmission line (DPMTL) terminated at both ends by linear circuits of very high frequency, including lumped elements, which can be passive and active. The diagnostic method proposed in this paper is based on a measurement test performed in the AC state. To write the diagnostic equations, the DPMTL is described by the chain equations in the frequency domain. For each considered fault, the line is divided into a cascade-connection of two lines, and a set of the diagnostic equations is written, taking into account basic circuit laws and the DPMTL description. This set includes nonlinear complex equations in two unknown real variables consisting of the distance from the beginning of the line to the point where it occurs and the fault value. To solve these equations, a numerical method has been developed. The procedure is applied to the possible soft shorts that can occur between all pairs of the line conductors, and the actual fault is selected. The method has also been adapted to the detection and location of open faults in DPMTL. Numerical examples, including three-conductor and five-conductor transmission lines, show that the diagnostic method is effective and very fast, and the CPU time does not exceed one second.

Switch Open-Fault Detection for a Three-Phase Hybrid Active Neutral-Point-Clamped Rectifier

This paper proposes a fault-detection method for open-switch failures in hybrid active neutral-point-clamped (HANPC) rectifiers. The basic HANPC topology comprises two SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) and four Si insulated-gate bipolar transistors (IGBTs). A three-phase rectifier system using the HANPC topology can produce higher efficiency and lower current harmonics. An open-switch fault in a HANPC rectifier can be a MOSFET or IGBT fault. In this work, faulty cases of six different switches are analyzed based on the current distortion in the stationary reference frame. Open faults in MOSFET switches cause immediate and remarkable current distortions, whereas, open faults in IGBT switches are difficult to detect using conventional methods. To detect an IGBT fault, the proposed detection method utilizes some of the reactive power in a certain period to make an important difference, using the direct-quadrant (dq)-axis current information derived from the three-phase current. Thus, the proposed detection method is based on three-phase current measurements and does not use additional hardware. By analyzing the individual characteristics of each switch failure, the failed switch can be located exactly. The effectiveness and feasibility of the proposed fault-detection method are verified through PSIM simulations and experimental results.

Design of Low Power 6T Sram with and without ROFs

An aggressive scaling in size and the increasing number of the transistor count are the important challenge of the design of Integrated Circuit (IC). In the same manner interconnection lines and resistive opens also became a major problem in present nanometer technology. The resistive open faults [ROFs] represent degradation [1] in connectivity’s within a circuit’s interconnections because of unavoidable manufacturing failures present in both current and future developing technologies. The resistive open fault [ROF] is an imperfect circuit connection that can be modelled as a defect resistors between two nodes of the circuit. The Resistive open faults [2] not causes the functionality of the circuit instantly. But, it causes the delay faults. In this research proposal, the impact of resistive open faults measured in 6-Transistors (6T) Static RAM memory cell design. The proposed 6T Static RAM memory cell implemented in 45nm technology by using Cadence Virtuoso library. The main goal of this proposed research work is to analise the effect of resistive open faults and how it reduce delay and power of 6T Static RAM cell. The resultant outputs of proposed 6T SRAM cell operation with and without ROFs will be compared.

Electric Field Assisted Self-Healing of Open Circuits with Conductive Particle-Insulating Fluid Dispersions: Optimizing Dispersion Concentration

Open circuit faults in electronic systems are a common failure mechanism, particularly in large area electronic systems such as display and image sensor arrays, flexible electronics and wearable electronics. To address this problem several methods to self heal open faults in real time have been investigated. One approach of interest to this work is the electric field assisted self-healing (eFASH) of open faults. eFASH uses a low concentration dispersion of conductive particles in an insulating fluid that is packaged over the interconnect. The electric field appearing in the open fault in a current carrying interconnect polarizes the conductive particles and chains them up to create a heal. This work studies the impact of dispersion concentration on the heal time, heal impedance and cross-talk when eFASH is used for self-healing. Theoretical predictions are supported by experimental evidence and an optimum dispersion concentration for effective self-healing is identified.

Impact of Resistive Open Faults on Inverter Chain and 7t Sram

An aggressive scaling of the technology and the increasing the number of the transistor counts are the major challenge of the design of the Integrated Circuit (IC). As well as interconnection lines and resistive opens have become a problem in modern nanometre technologies. The resistive open faults denote degradation in the connectivity within a circuit’s interconnects because of unavoidable manufacturing failures in both current and developing technologies. The resistive open fault is an imperfect circuit connection that can be modelled as a defect resistor between two circuit nodes. The Resistive open faults will not cause function fault immediately. But, it will cause the delay fault and cannot employ the design of voltage to survey. In this research, find the impact of resistive open fault in the 7- Transistor (7T) SRAM cell design and inverter chain. The proposed 7T SRAM cell design and inverter chain is implemented in 45nm technology with cadence library. The main objective of this proposed research work is to efficiently detect impact of resistive open faults and reduces delay and static and dynamic power of 7T SRAM cell design and inverter chain.