Clock Network Synthesis with Concurrent Gate Insertion

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-17752-1_23 ◽

2011 ◽

pp. 228-237

Author(s):

Jingwei Lu ◽

Wing-Kai Chow ◽

Chiu-Wing Sham

Keyword(s):

Network Synthesis ◽

Clock Network

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Clock Network Synthesis Based on Clock Mesh Technology

Journal of Physics Conference Series ◽

10.1088/1742-6596/1345/4/042095 ◽

2019 ◽

Vol 1345 ◽

pp. 042095

Author(s):

Yi Tao ◽

YuJing Li ◽

Wu Yang

Keyword(s):

Network Synthesis ◽

Clock Network

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Evolving challenges and techniques for nanometer SoC clock network synthesis

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2014.7021158 ◽

2014 ◽

Cited By ~ 3

Author(s):

Subhendu Roy ◽

Pavlos M. Mattheakis ◽

Laurent Masse-Navette ◽

David Z. Pan

Keyword(s):

Network Synthesis ◽

Clock Network

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The future of clock network synthesis

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2011.6105339 ◽

2011 ◽

Cited By ~ 1

Author(s):

Cliff Sze

Keyword(s):

Network Synthesis ◽

Clock Network ◽

The Future

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An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2110591 ◽

2011 ◽

Vol 30 (7) ◽

pp. 1045-1057

Author(s):

Sheng Chou ◽

Cheng-Shen Han ◽

Po-Kai Huang ◽

Ko-Fan Tien ◽

Tsung-Yi Ho

Keyword(s):

Network Synthesis ◽

Clock Network ◽

Latency Range

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Variation tolerant buffered clock network synthesis with cross links

Proceedings of the 2006 international symposium on Physical design - ISPD '06 ◽

10.1145/1123008.1123038 ◽

2006 ◽

Cited By ~ 27

Author(s):

Anand Rajaram ◽

David Z. Pan

Keyword(s):

Network Synthesis ◽

Clock Network ◽

Cross Links

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ISPD 2010 high performance clock network synthesis contest

Proceedings of the 19th international symposium on Physical design - ISPD '10 ◽

10.1145/1735023.1735058 ◽

2010 ◽

Cited By ~ 40

Author(s):

C. N. Sze

Keyword(s):

High Performance ◽

Network Synthesis ◽

Clock Network

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A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness

Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14 ◽

10.1145/2591513.2591584 ◽

2014 ◽

Cited By ~ 1

Author(s):

Rickard Ewetz ◽

Anirudh Udupa ◽

Ganesh Subbarayan ◽

Cheng-Kok Koh

Keyword(s):

Network Synthesis ◽

Cross Link ◽

Clock Network

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Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength

Proceedings of the 2020 on Great Lakes Symposium on VLSI ◽

10.1145/3386263.3406949 ◽

2020 ◽

Author(s):

Wei Wang ◽

Vasilis F. Pavlidis ◽

Yuanqing Cheng

Keyword(s):

Network Synthesis ◽

3D Ics ◽

Clock Network ◽

Zero Skew

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Cross link insertion for improving tolerance to variations in clock network synthesis

Proceedings of the 2011 international symposium on Physical design - ISPD '11 ◽

10.1145/1960397.1960407 ◽

2011 ◽

Cited By ~ 19

Author(s):

Tarun Mittal ◽

Cheng-Kok Koh

Keyword(s):

Network Synthesis ◽

Cross Link ◽

Clock Network

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A dual-MST approach for clock network synthesis

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419838 ◽

2010 ◽

Author(s):

Jingwei Lu ◽

Wing-Kai Chow ◽

Chiu-Wing Sham ◽

Evangeline F.Y. Young

Keyword(s):

Network Synthesis ◽

Clock Network

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