2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
Latest Publications

TOTAL DOCUMENTS

169

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781424457656

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

PS-FPG: Pattern selection based co-design of floorplan and Power/Ground network with wiring resource optimization

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419785 ◽

2010 ◽

Cited By ~ 1

Author(s):

Li Li ◽

Yuchun Ma ◽

Ning Xu ◽

Yu Wang ◽

Xianlong Hong

Keyword(s):

Resource Optimization ◽

Pattern Selection

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A fast heuristic scheduling algorithm for periodic ConcurrenC models

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419901 ◽

2010 ◽

Author(s):

Weiwei Chen ◽

Rainer Doemer

Keyword(s):

Scheduling Algorithm ◽

Heuristic Scheduling

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A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419852 ◽

2010 ◽

Cited By ~ 3

Author(s):

Zhigang Hao ◽

Guoyong Shi

Keyword(s):

Statistical Analysis ◽

Symbolic Computation ◽

Mesh Networks ◽

Multiple Sources

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Improved clock-gating control scheme for transparent pipeline

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419847 ◽

2010 ◽

Cited By ~ 3

Author(s):

Jung Hwan Choi ◽

Byung Guk Kim ◽

Aurobindo Dasgupta ◽

Kaushik Roy

Keyword(s):

Clock Gating ◽

Control Scheme

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Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419889 ◽

2010 ◽

Cited By ~ 1

Author(s):

Jungseob Lee ◽

Shi-Ting Zhou ◽

Nam Sung Kim

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Fault-tolerant resynthesis with dual-output LUTs

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419873 ◽

2010 ◽

Cited By ~ 12

Author(s):

Ju-Yueh Lee ◽

Yu Hu ◽

Rupak Majumdar ◽

Lei He ◽

Minming Li

Keyword(s):

Fault Tolerant

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Application-specific 3D Network-on-Chip design using simulated allocation

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419830 ◽

2010 ◽

Cited By ~ 4

Author(s):

Pingqiang Zhou ◽

Ping-Hung Yuh ◽

Sachin S. Sapatnekar

Keyword(s):

Network On Chip ◽

Chip Design ◽

3D Network ◽

On Chip ◽

Application Specific

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A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419897 ◽

2010 ◽

Cited By ~ 44

Author(s):

J. Singh ◽

K. Ramakrishnan ◽

S. Mookerjea ◽

S. Datta ◽

N. Vijaykrishnan ◽

...

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Tunnel Fet ◽

Sram Design

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Trace-based performance analysis framework for heterogeneous multicore systems

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419926 ◽

2010 ◽

Cited By ~ 5

Author(s):

Shih-Hao Hung ◽

Chia-Heng Tu ◽

Thean-Siew Soon

Keyword(s):

Performance Analysis ◽

Analysis Framework ◽

Multicore Systems ◽

Heterogeneous Multicore

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Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419860 ◽

2010 ◽

Author(s):

Chen-I Chung ◽

Shuo-Wen Chang ◽

Feng-Tso Chien ◽

Ching-Hwa Cheng

Keyword(s):

Delay Testing ◽

Calibration Technique ◽

Double Edge ◽

Fine Resolution

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2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

PS-FPG: Pattern selection based co-design of floorplan and Power/Ground network with wiring resource optimization

A fast heuristic scheduling algorithm for periodic ConcurrenC models

A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources

Improved clock-gating control scheme for transparent pipeline

Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors

Fault-tolerant resynthesis with dual-output LUTs

Application-specific 3D Network-on-Chip design using simulated allocation

A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Trace-based performance analysis framework for heterogeneous multicore systems

Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
Latest Publications