Efficient Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist - Skein

Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA-256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA-256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design.

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VLSI Design and Implementation of Combined Secure Hash Algorithm SHA-512

Recent Trends in Network Security and Applications - Communications in Computer and Information Science ◽

10.1007/978-3-642-14478-3_11 ◽

2010 ◽

pp. 105-113 ◽

Cited By ~ 1

Author(s):

R. Kayalvizhi ◽

R. Harihara Subramanian ◽

R. Girish Santhosh ◽

J. Gurubaran ◽

V. Vaidehi

Keyword(s):

Vlsi Design ◽

Design And Implementation ◽

Hash Algorithm ◽

Secure Hash Algorithm

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An Effective Framework for Chaotic Image Encryption Based on 3D Logistic Map

Security and Communication Networks ◽

10.1155/2018/8402578 ◽

2018 ◽

Vol 2018 ◽

pp. 1-11 ◽

Cited By ~ 7

Author(s):

Guodong Ye ◽

Kaixin Jiao ◽

Chen Pan ◽

Xiaoling Huang

Keyword(s):

Chaotic Map ◽

Logistic Map ◽

Security Analysis ◽

Three Dimensional ◽

Ecg Signal ◽

Hash Algorithm ◽

Plain Image ◽

Secure Hash Algorithm ◽

Low Sensitivity ◽

Encryption Method

In this paper, an effective framework for chaotic encryption based on a three-dimensional logistic map is presented together with secure hash algorithm-3 (SHA-3) and electrocardiograph (ECG) signal. Following the analysis of the drawbacks, namely, fixed key and low sensitivity, of some current algorithms, this work tries to solve these two problems and includes two contributions: (1) removal of the phenomenon of summation invariance in a plain-image, for which SHA-3 is proposed to calculate the hash value for the plain-image, with the results being employed to influence the initial keys for chaotic map; (2) resolution of the problem of fixed key by using an ECG signal, that can be different for different subjects or different for same subject at different times. The Wolf algorithm is employed to produce all the control parameters and initial keys in the proposed encryption method. It is believed that combining with the classical architecture of permutation-diffusion, the summation invariance in the plain-image and shortcoming of a fixed key will be avoided in our algorithm. Furthermore, the experimental results and security analysis show that the proposed encryption algorithm can achieve confidentiality.

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