DSP–FPGA-Based Parallel Architecture for Acquisition and Compression of Instrumented Pipeline Inspection Gauge Data in Real Time

2013 ◽  
pp. 255-261
Author(s):  
Sushil Kumar Bahuguna ◽  
Sangeeta Dhage ◽  
Siddhartha Mukhopadhyay ◽  
Y. K. Taly
Keyword(s):  
Real Time ◽  
Parallel Architecture ◽  
Pipeline Inspection ◽  
Gauge Data

Method and parallel architecture for extracting the image fractal dimension in real time

1998 ◽  
Author(s):  
Xiangdong Chen ◽  
Wensen Chang ◽  
Zheng Gao
Keyword(s):  
Fractal Dimension ◽  
Real Time ◽  
Parallel Architecture

A hardware-efficient parallel architecture for real-time blob analysis based on run-length code

2017 ◽  
Vol 15 (3) ◽  
pp. 657-672 ◽  
Author(s):  
Bingjie Li ◽  
Cunguang Zhang ◽  
Bo Li ◽  
Hongxu Jiang ◽  
Qizhi Xu
Keyword(s):  
Real Time ◽  
Parallel Architecture ◽  
Run Length ◽  
Blob Analysis ◽  
Length Code

Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA

2018 ◽  
Vol 103 (3) ◽  
pp. 1941-1963 ◽  
Author(s):  
Deepak Kumar Gupta ◽  
Vijay Kumar Gupta ◽  
Mahesh Chandra ◽  
Gaurav Verma
Keyword(s):  
Real Time ◽  
Parallel Architecture ◽  
Speech Signals

An Application Case of Transferring Intelligent Well System Triple-Gauge Data into Real-Time Flow Allocation Results

2011 ◽  
Author(s):  
Kai Sun ◽  
Oluwole Ayodotun Omole ◽  
Luigi Alfonso Saputelli ◽  
Fabio Alberto Gonzalez
Keyword(s):  
Real Time ◽  
Time Flow ◽  
Gauge Data

Transferring Intelligent-Well-System Triple-Gauge Data Into Real-Time Flow Allocation

2012 ◽  
Vol 27 (02) ◽  
pp. 264-281 ◽  
Author(s):  
Kai Sun ◽  
Oluwole Omole ◽  
Luigi Saputelli ◽  
Fabio Gonzalez
Keyword(s):  
Real Time ◽  
Time Flow ◽  
Gauge Data

scholarly journals A Parallel Architecture for the Partitioning Around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4129 ◽  
Author(s):  
Hassan Mushtaq ◽  
Sajid Gul Khawaja ◽  
Muhammad Usman Akram ◽  
Amanullah Yasin ◽  
Muhammad Muzammal ◽  
...  
Keyword(s):  
Computational Complexity ◽  
Real Time ◽  
Parallel Architecture ◽  
Partitioning Around Medoids ◽  
Proposed Model ◽  
Data Points ◽  
Data Objects ◽  
Natural Groups ◽  
Multiple Processing ◽  
Multi Core Processor

Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of clustering widely used for objects categorization, image analysis, bioinformatics and data compression, but due to its high time complexity, the PAM algorithm cannot be used with large datasets or in any embedded or real-time application. In this work, we propose a simple and scalable parallel architecture for the PAM algorithm to reduce its running time. This architecture can easily be implemented either on a multi-core processor system to deal with big data or on a reconfigurable hardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering applications. Our proposed model partitions data equally among multiple processing cores. Each core executes the same sequence of tasks simultaneously on its respective data subset and shares intermediate results with other cores to produce results. Experiments show that the computational complexity of the PAM algorithm is reduced exponentially as we increase the number of cores working in parallel. It is also observed that the speedup graph of our proposed model becomes more linear with the increase in number of data points and as the clusters become more uniform. The results also demonstrate that the proposed architecture produces the same results as the actual PAM algorithm, but with reduced computational complexity.

scholarly journals High dynamic range, Interferences Tolerant, Digital Receivers for Radioastronomy: Results and Projects at Paris and Nanay Observatory

2002 ◽  
Vol 199 ◽  
pp. 506-507
Author(s):  
Carlo Rosolen ◽  
Alain Lecacheux ◽  
Eric Gerard ◽  
Vincent Clerc ◽  
Laurent Denis
Keyword(s):  
Real Time ◽  
Dynamic Range ◽  
Block Diagram ◽  
Low Frequency ◽  
Parallel Architecture ◽  
Digital Signal ◽  
High Dynamic Range ◽  
Dsp System ◽  
High Dynamic ◽  
Digital Receivers

Radio astronomy in the decameter to centimeter wavelength range is facing new challenges because of man made interferences due to increasing needs in telecommunications. At the Radioastronomy department of Paris Meudon Observatory, we have been working since four years on high dynamic range digital receivers based on Digital Signal Processors (DSP). The first achievement is a digital spectro- polarimeter devoted to spectroscopy of astrophysical radiation in decameter range, now in operation at the Nancay Decameter array. The block diagram of the receiver includes a high dynamic range analogue section followed by a 12 bits analogue to digital converter. The digital part makes use of high power, programmable digital circuits for signal processing, arranged in a dedicated parallel architecture, able to compute in real time the power spectrum and the correlation of the input signals. This receiver was also used, as spectrometer backend, at Nancay decimetric radiotelescope and has performed very well in the presence of very strong interferences. We are presently working on a new digital receiver with broader bandwidth. The objective is 2 × 25 MHz band with at least 60 dB dynamic range. This new receiver will use additional computation power in order to recognise and avoid man made interferences which corrupt the radio astronomical signal. At the Nancay Radioastronomy Observatory, we have started to develop a new digital configurable receiver with 8 times 25 MHz band and ten thousand channels. For low frequency radioastronomy, direct spectrum computation technique is really powerful and offers new capabilities for real time interferences excision. Fig. 1 shows pulsar observations in the presence of interference made with the DSP receiver on the UTR-2 radiotelescope. Fig. 2 shows the effect of satellite interfernce on OH observations made with the Nancay telescope. Fig. 3 shows the block diagram of the DSP system and demonstrates how offline excision of interference in the frequency time-domain enables recovery of the signal. The final spectrum had 960 minutes integration on and off source and took 8045 minutes of procession on a 450 MHz Pentium II.

Sign in / Sign up

Export Citation Format

Share Document