Design of High-Order Extrapolated Impulse Response FIR Filters with Signed Powers-of-Two Coefficients

2011 ◽  
Vol 30 (5) ◽  
pp. 963-985 ◽  
Author(s):  
Yanfei Cao ◽  
Kai Wang ◽  
Wenjiang Pei ◽  
Yujie Liu ◽  
Yifeng Zhang
Keyword(s):  
Impulse Response ◽  
High Order ◽  
Fir Filters

A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm

2019 ◽  
Vol 330 ◽  
pp. 425-436 ◽  
Author(s):  
Giovanny Sanchez ◽  
Carlos Diaz ◽  
Juan-Gerardo Avalos ◽  
Luis Garcia ◽  
Angel Vazquez ◽  
...  
Keyword(s):  
Adaptive Algorithm ◽  
High Order ◽  
Fir Filters ◽  
Neuromorphic Architecture

Comparison of Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) Filters in Cardiac Optical Mapping Records

2021 ◽  
pp. 207-224
Author(s):  
David Rivas-Lalaleo ◽  
Sergio Muñoz-Romero ◽  
Monica Huerta ◽  
Víctor Bautista-Naranjo ◽  
Jorge García-Quintanilla ◽  
...  
Keyword(s):  
Impulse Response ◽  
Optical Mapping ◽  
Finite Impulse Response ◽  
Infinite Impulse Response ◽  
Fir Filters

Extrapolated impulse response FIR filters

1990 ◽  
Vol 37 (12) ◽  
pp. 1548-1551 ◽  
Author(s):  
Y.C. Lim ◽  
B. Liu
Keyword(s):  
Impulse Response ◽  
Fir Filters

Multiplierless Multiple-Stage Cascaded FIR Filter Design

2014 ◽  
Vol 24 (01) ◽  
pp. 1550011
Author(s):  
Wenbin Ye
Keyword(s):  
Impulse Response ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Single Stage ◽  
Fir Filters ◽  
Hardware Cost ◽  
Stage Design ◽  
Design Time ◽  
Fir Filter Design ◽  
Novel Algorithm

It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing algorithm in terms of hardware cost and the design time is also saved.

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