<title>FPGA implementation of high-order FIR filters by requantizing the input data stream</title>

This article is devoted to solving some of the issues of distributed multimedia data display on large screens. In particular, we consider the problem of synchronization of the process of parallel rendering and output of video fragments to the appropriate modules of multiscreen display systems. Proposed synchronization algorithm and its implementation using graphics accelerators, provides visual continuity of dynamic scenes when displayed on a multiscreen. The problems of managing distributed input data stream for multiscreen display are considered.

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Accessing Remote Locations

Building and Managing Enterprise-Wide Portals ◽

10.4018/978-1-59140-661-7.ch010 ◽

2011 ◽

pp. 173-185

Author(s):

Jana Polgar ◽

Robert Mark Braum ◽

Tony Polgar

Keyword(s):

Web Services ◽

Web Service ◽

Data Stream ◽

Input Data ◽

Response Times ◽

Alternative Solution ◽

Raw Data ◽

Remote Locations ◽

The Web ◽

Server Process

Most of today’s portal implementations provide a model that facilitates plugging various components (portlets) into the portal infrastructure. Portlets run locally on the portal server, process input data, and render output. A local portlet and a good caching strategy for the content improves the response times, performance, and scalability of portal systems. However, very often we need to access remote Web services. One solution is to use a local portlet to access a remote Web service via its interface, obtain the required results as a raw data stream, and locally render the results in a fragment. This approach is relevant for data-oriented Web services. An alternative solution is to equip the Web service with an additional interface in the form of a portlet. When the Web service is called, it returns the entire portlet instead of raw data. This approach is suitable for presentation-oriented Web services.

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FPGA Implementation of an Optimized Coefficients Pulse Shaping FIR Filters

2006 IEEE International Conference on Semiconductor Electronics ◽

10.1109/smelec.2006.381102 ◽

2006 ◽

Cited By ~ 1

Author(s):

Mohamed Almahdi Eshtawie ◽

Masuri Othman

Keyword(s):

Pulse Shaping ◽

Fpga Implementation ◽

Fir Filters

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NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS

Journal of Circuits System and Computers ◽

10.1142/s0218126604001970 ◽

2004 ◽

Vol 13 (06) ◽

pp. 1233-1249 ◽

Cited By ~ 6

Author(s):

WEI WANG ◽

M. N. S. SWAMY ◽

M. O. AHMAD

Keyword(s):

Power Efficiency ◽

Filter Design ◽

Finite Impulse Response ◽

Chinese Remainder Theorem ◽

Low Cost ◽

Digital Signal ◽

Number System ◽

Residue Number System ◽

Fpga Implementation ◽

Fir Filters

Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

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