Enhanced Electrical Properties of La $$_{0.7}$$ 0.7 (Ca $$_{0.2}$$ 0.2 Sr $$_{0.1}$$ 0.1 ) MnO $$_{3}$$ 3 Polycrystalline Composites with Ag Addition

2015 ◽  
Vol 180 (5-6) ◽  
pp. 356-362 ◽  
Author(s):  
Xuejiao Yue ◽  
Yanhong Zhan ◽  
Xiang Liu ◽  
Gang Gu ◽  
Qiangshen Wang ◽  
...  
2010 ◽  
Vol 25 (2) ◽  
pp. 391-395 ◽  
Author(s):  
Chien-Neng Liao ◽  
Yen-Chun Huang

SnTe is the most common compound formed at the bismuth telluride/metal soldered junction of thermoelectric modules. It affects the mechanical and electrical properties of the soldered junction. In the study we investigate the growth of SnTe compound during reaction between molten Sn–3.5Ag solder and tellurium at 250 °C. We found that the growth of SnTe is suppressed by Ag–Te bilayer compounds that block further reaction between liquid Sn and Te. With increasing reaction time, the SnTe morphology becomes rough as a result of coarsening of SnTe grains. The growth of SnTe grains follows the conservative ripening kinetics with the mean particle size proportional to one-third power of reaction time.


2015 ◽  
Vol 349 ◽  
pp. 983-987 ◽  
Author(s):  
Xuepeng Yin ◽  
Xiang Liu ◽  
Yanhong Zhan ◽  
Hui Zhang ◽  
Qingming Chen

2010 ◽  
Vol 21 (3) ◽  
pp. 242-245 ◽  
Author(s):  
Joseph Lik Hang Chau ◽  
Yu-Hsien Chou ◽  
Chi-San Chen ◽  
Chih-Chao Yang

Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


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