scholarly journals KL_GA: an application mapping algorithm for mesh-of-tree (MoT) architecture in network-on-chip design

2015 ◽  
Vol 71 (11) ◽  
pp. 4056-4071 ◽  
Author(s):  
Juan Fang ◽  
Lu Yu ◽  
Sitong Liu ◽  
Jiajia Lu ◽  
Tan Chen
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Mapping Algorithm ◽  
Application Mapping ◽  
On Chip

A new application mapping algorithm for mesh based Network-on-Chip design

2010 ◽  
Author(s):  
Pradip Kumar Sahu ◽  
Nisarg Shah ◽  
Kanchan Manna ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Mapping Algorithm ◽  
Application Mapping ◽  
On Chip

Dynamic Application Mapping Algorithm for Wireless Network-on-Chip

2015 ◽  
Author(s):  
Amin Rezaei ◽  
Masoud Daneshtalab ◽  
Danella Zhao ◽  
Farshad Safaei ◽  
Xiaohang Wang ◽  
...  
Keyword(s):  
Wireless Network ◽  
Network On Chip ◽  
Mapping Algorithm ◽  
Application Mapping ◽  
On Chip

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

scholarly journals Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design

2014 ◽  
Vol 99 (3) ◽  
pp. 8-22 ◽  
Author(s):  
Pradip KumarSahu ◽  
Kanchan Manna ◽  
Tapan Shah ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Application Mapping ◽  
On Chip
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