Power is a major constraint in Digital VLSI
circuits, due to reduction in sizes of Metal Oxide Semiconductor
(MOS) transistors are scaling down. Low-power technologies are
used to diminish the power utilization be able to be classified as
Sub-threshold CMOS and Adiabatic logic tachniques. In,
Sub-threshold CMOS defines a system which reduces the power
utilization to inferior than the threshold voltage of a MOS
Device, where as Adiabatic logic circuit is a method which
minimizes the energy usage through suppress the applied voltage
to the resistance of a given VLSI design. This effort deals to offer
a subthreshold adiabatic logic circuit of low power CMOS
circuits that uses 2φ clocking subthreshold Adiabatic Logic. The
digital circuits were designed in HSPICE using 0.18 μm CMOS
standard process technology. It is evident from the results that
the 2φ Clocking Subthreshold Adiabatic design is beneficial in
major application where power starving is of major significance
at the same time as in elevated its performance efficiency in
DSP processor IC, System on chip, Network on chip and High
speed digital ICs.
Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic