Development of real-time object motion estimation from single camera

In the video encoding system, motion estimation plays an important role at the front-end of encoder, which can eliminate inter redundancy efficiently and improve encoding efficiency. However, traditional motion estimation algorithm can’t be used in real-time application like video monitoring due to its computational complexity. In order to improve real-time efficiency, an improved motion estimation algorithm is proposed in this paper. The essential ideas consist of early termination rules, prediction of initial search point, and determination of motion type. Furthermore, our algorithm adopts different search patterns for certain motion activity. Experimental result shows that the improved algorithm reduces the computation time significantly while maintaining the image quality, and satisfies real time requirement in monitoring system.

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Motion Estimation Architecture Using Efficient Adder-Compressors for HDTV Video Coding

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v5i1.312 ◽

2010 ◽

Vol 5 (1) ◽

pp. 78-88 ◽

Cited By ~ 1

Author(s):

Marcelo Porto ◽

André Silva ◽

Sergo Almeida ◽

Eduardo Da Costa ◽

Sergio Bampi

Keyword(s):

Motion Estimation ◽

Real Time ◽

Search Algorithm ◽

Absolute Difference ◽

High Definition ◽

Case Processing ◽

Worst Case ◽

Average Case ◽

High Definition Television ◽

Internal Structures

This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation (ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main characteristic of the proposed architecture is the large amount of Processing Units (PUs) that are used to calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs are composed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to work with HDTV (High Definition Television) videos in real time at 30 frames per second. These adder compressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, using adder compressors, were applied to the ME architecture. The implemented architecture was described in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC 0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC architecture reach the best performance result and enable gains of 12% in terms of processing rate. The architecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65 frames per second, and it can process 269 HDTV frames per second in the average case.

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