A Survey on Domain-Specific Memory Architectures

The never-ending demand for high performance and energy efficiency is pushing designers towards an increasing level of heterogeneity and specialization in modern computing systems. In such systems, creating efficient memory architectures is one of the major opportunities for optimizing modern workloads (e.g., computer vision, machine learning, graph analytics, etc.) that are extremely data-driven. However, designers demand proper design methods to tackle the increasing design complexity and address several new challenges, like the security and privacy of the data to be elaborated.This paper overviews the current trend for the design of domain-specific memory architectures. Domain-specific architectures are tailored for the given application domain, with the introduction of hardware accelerators and custom memory modules while maintaining a certain level of flexibility. We describe the major components, the common challenges, and the state-of-the-art design methodologies for building domain-specific memory architectures. We also discuss the most relevant research projects, providing a classification based on our main topics.

Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification

This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades, but their costs are increasingly hard to cope with. Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes. This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process variations; (3) temperature variations; (4) circuit aging. Besides addressing energy-efficiency and all the mentioned robustness aspects, this work also approaches some of the state-of-the-art tools available to deal with asynchronous design, and points to desirable research development to be conducted in these subjects in the future.

A Survey on System-Level Design of Neural Network Accelerators

In this paper, we present a brief survey on the system-level optimizations used for convolutional neural network (CNN) inference accelerators. For the nested loop of convolutional (CONV) layers, we discuss the effects of loop optimizations such as loop interchange, tiling, unrolling and fusion on CNN accelerators. We also explain memory optimizations that are effective with the loop optimizations. In addition, we discuss streaming architectures and single computation engine architectures that are commonly used in CNN accelerators. Optimizations for CNN models are briefly explained, followed by the recent trends and future directions of the CNN accelerator design.

Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present

Modern cryptographic circuits are increasingly demanding security requirements. Since its invention, power analysis attacks are a threat to the security of such circuits. In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. This work presents a brief survey of countermeasures to help designers to find good solutions for the design of secure cryptographic systems. A summary is highlighted to compare the pros and cons of the approaches to help designers choose a better solution, or even provide subsidies so that new solutions can be proposed.

Programmable Data Planes meets In-Network Computing: A Review of the State of the Art and Prospective Directions

Improving network traffic in networks is one of the concerns between networking researchers and network operators since the architecture of modern networks still faces challenges to process large data traffic without the cost of consuming a significant amount of resources not related to computing specifically. On the other hand, network programmability has enabled the development of new applications and network services, from software-defined networking to domain-specific languages created to program network devices and specify their behavior. The development of programmable hardware and hardware accelerators like FPGAs, GPUs, and CPUs help this new paradigm go one step further. Use the artifact of programmability of these devices to solve problems, such as improve the processing of data traffic is the key of in-network computing. It offers the opportunity to execute programs typically running on end-hosts within programmable network devices already incorporated on the network, thus being capable of provides a reduction on the in-network processing load and requires no extra cost, since operations can be concluded using a fewer amount of devices of the network and no extra device are needed. In this paper, we survey in-network computing, as well as we suggest classifying related works to in-network computing according to the hardware accelerator used. Also, we discuss challenges and research directions.

3-D TCAD Monte Carlo Device Simulator: State-of-the-art FinFET Simulation

This work presents a comprehensive description of an in-house 3D Monte Carlo device simulator for physical mod-eling of FinFETs. The simulator was developed to consider var-iability effects properly and to be able to study deeply scaled devices operating in the ballistic and quasi-ballistic regimes. The impact of random dopants and trapped charges in the die-lectric is considered by treating electron-electron and electron-ion interactions in real-space. Metal gate granularity is in-cluded through the gate work function variation. The capability to evaluate these effects in nanometer 3D devices makes the pre-sented simulator unique, thus advancing the state-of-the-art. The phonon scattering mechanisms, used to model the transport of electrons in pure silicon material system, were validated by comparing simulated drift velocities with available experi-mental data. The proper behavior of the device simulator is dis-played in a series of studies of the electric potential in the device, the electron density, the carrier's energy and velocity, and the Id-Vg and Id-Vd curves.

Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs

In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations. The impact of the substrate bias is observed for a set of values ranging from -3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with different types of ground plane (GP-P and GPN) and without GPhave been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.

A Survey on Microtransformers

The miniaturization of magnetic devices is a subject of enduring interest, since inductors and transformers of very small dimensions are constantly being required for integration into microchips and electrical circuit boards. The main objective of this survey is to supply a compilation of the published research on microtransformers, and to work as a support material, helping in the choice of the most appropriate technology and device configuration for a particular application. The text describes the historical development of microtransformers, the structures in which these devices might be assembled, the various proposed geometries, the fabrication processes, and the type of core used. A brief discussion of equivalent circuit modeling is presented. The current state of the technology in relation to commercial devices is then examined, pointing out some unsolved problems that warrant further studies.

A Survey on Security Mechanisms for NoC-based Many-Core SoCs

The adoption of many-cores systems introduces the concern for data protection as a critical design requirement due to the resource sharing and the simultaneous executions of several applications on the platform. A secure application that processes sensitive data may have its security harmed by a malicious process. The literature contains several proposals to protect many-cores against attacks, focusing on the protection of the application execution or the access to shared memories. However, there is a gap to be fulfilled: a solution covering the entire application lifetime, including its admission, execution, and peripheral's access. This survey discusses three security-related issues: the secure admission of applications, the prevention of resource sharing during their execution, and the safe access to external devices. This survey concludes with an evaluation of the studied methods, pointing out directions and research opportunities.