CNTFET Design of a Multiple-Port Ternary Register File

Microelectronics Journal ◽

10.1016/j.mejo.2021.105076 ◽

2021 ◽

pp. 105076

Author(s):

A. Mohammaden ◽

M.E. Fouda ◽

Ihsen Alouani ◽

Lobna A. Said ◽

Ahmed G. Radwan

Keyword(s):

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Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00127 ◽

2009 ◽

Vol 31 (1) ◽

pp. 127-132

Author(s):

Zhi-Xiong ZHOU ◽

Hu HE ◽

Xu YANG ◽

Yan-Jun ZHANG ◽

Yi-He SUN

Keyword(s):

Scheduling Algorithm ◽

Instruction Scheduling ◽

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Active-Cycle Based Register File Design for Reduced Ports and Energy

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00299 ◽

2009 ◽

Vol 31 (2) ◽

pp. 299-308 ◽

Author(s):

Yu-Lai ZHAO ◽

Xian-Feng LI ◽

Dong TONG ◽

Han-Xin SUN ◽

Jie CHEN ◽

...

Keyword(s):

Register File ◽

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Register/ file/ cache microarchitecture study using VHDL

Proceedings of the 24th annual international symposium on Microarchitecture - MICRO 24 ◽

10.1145/123465.123510 ◽

1991 ◽

Author(s):

Samarina Makhdoom ◽

Daniel Tabak ◽

Richard Auletta

Keyword(s):

Register File ◽

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24.4 A 5nm [email protected] and [email protected] 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9366000 ◽

2021 ◽

Author(s):

Hidehiro Fujiwara ◽

Yi-Hsin Nien ◽

Chih-Yu Lin ◽

Hsien-Yu Pan ◽

Hao-Wen Hsu ◽

...

Keyword(s):

Standard Cell ◽

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A 0.13 μm 6 GHz 256×32b leakage-tolerant register file

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) ◽

10.1109/vlsic.2001.934182 ◽

2002 ◽

Author(s):

R. Krishnamurthy ◽

A. Alvandpour ◽

G. Balamurugan ◽

N. Shanbhagh ◽

K. Soumyanath ◽

...

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An Area-Efficient Approach to Improving Register File Reliability against Transient Errors

21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07) ◽

10.1109/ainaw.2007.78 ◽

2007 ◽

Author(s):

Mallik Kandala ◽

Wei Zhang ◽

Laurence T. Yang

Keyword(s):

Register File ◽

Efficient Approach ◽

Transient Errors ◽

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Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

Proceedings of the 45th annual conference on Design automation - DAC '08 ◽

10.1145/1391469.1391488 ◽

2008 ◽

Author(s):

Houman Homayoun ◽

Sudeep Pasricha ◽

Mohammad Makhzan ◽

Alex Veidenbaum

Keyword(s):

Register File ◽

Frequency Scaling ◽

Embedded Processor ◽

Processor Performance

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A scalable register file architecture for dynamically scheduled processors

Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique ◽

10.1109/pact.1996.552666 ◽

2002 ◽

Author(s):

S. Wallace ◽

N. Bagherzadeh

Keyword(s):

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Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28nm UTBB-FDSOI

Microelectronics Journal ◽

10.1016/j.mejo.2016.10.002 ◽

2016 ◽

Vol 57 ◽

pp. 76-86 ◽

Author(s):

Sébastien Bernard ◽

Marc Belleville ◽

Jean-Didier Legat ◽

Alexandre Valentian ◽

David Bol

Keyword(s):

Register File ◽

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Register File Criticality and Compiler Optimization Effects on Embedded Microprocessors Reliability

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2017.2705150 ◽

2017 ◽

pp. 1-1 ◽

Author(s):

Filipe Lins ◽

Lucas Tambara ◽

Fernanda Lima Kastensmidt ◽

Paolo Rech

Keyword(s):

Compiler Optimization ◽

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