Performance Analysis of Secure Elements for IoT

New protocol stacks provide wireless IPv6 connectivity down to low power embedded IoT devices. From a security point of view, this leads to high exposure of such IoT devices. Consequently, even though they are highly resource-constrained, these IoT devices need to fulfil similar security requirements as conventional computers. The challenge is to leverage well-known cybersecurity techniques for such devices without dramatically increasing power consumption (and therefore reducing battery lifetime) or the cost regarding memory sizes and required processor performance. Various semiconductor vendors have introduced dedicated hardware devices, so-called secure elements that address these cryptographic challenges. Secure elements provide tamper-resistant memory and hardware-accelerated cryptographic computation support. Moreover, they can be used for mutual authentication with peers, ensuring data integrity and confidentiality, and various other security-related use cases. Nevertheless, publicly available performance figures on energy consumption and execution times are scarce. This paper introduces the concept of secure elements and provides a measurement setup for selected individual cryptographic primitives and a DTLS handshake over CoAPs in a realistic use case. Consequently, the paper presents quantitative results for the performance of five secure elements. Based on these results, we discuss the characteristics of the individual secure elements and supply developers with the information needed to select a suitable secure element for a specific application.

Dynamic Biasing for Improved On-Orbit Total-Dose Lifetimes of Commercial Electronic Devices

The survivability of microelectronic devices in ionizing radiation environments drives spacecraft design, capability, mission scope, and cost. This work exploits the periodic nature of many space radiation environments to extend device lifetimes without additional shielding or modifications to the semiconductor architecture. We propose a technique for improving component lifetimes through reduced total-dose accumulation by modulating device bias during periods of intense irradiation. Simulation of this ``dynamic biasing" technique applied to single-transistor devices in a typical low-Earth orbit results in an increase of component life from 114 days to 477 days (318% improvement) at the expense of 5% down time (95% duty cycle). The biasing technique is also experimentally demonstrated using gamma radiation to study three commercial devices spanning a range of integrated circuit complexity in 109 rad/min and 256 rad/min dose rate conditions. The demonstrated improvements in device lifetimes using the proposed dynamic biasing technique lays a foundation for more effective use of modern microelectronics for space applications. Analogous to the role real-time temperature monitoring plays in maximizing modern processor performance, the proposed dynamic biasing technique is a means of intelligently responding to the radiation environment and capable of becoming an integral tool in optimizing component lifetimes in space.

Processor performance metrics analysis and implementation for MIPS using an open source OS

<p><span>Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varing load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction exxecution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twenty-seven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analysing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterisation and kernel profiling.</span></p>

Optimization Analysis of Tennis Players’ Physical Fitness Index Based on Data Mining and Mobile Computing

Tennis is a very explosive, continuous, and intense sport, including many continuous short-term explosive actions. It has the characteristics of short-term, high-intensity, high-density training, and it belongs to the category of purely competitive skills. In the competition, athletes must maintain good physical condition, physical fitness, and long-term endurance in order to demonstrate outstanding technical and tactical skills. Therefore, this paper proposes a mobile processor performance data mining framework MobilePerfMiner, which uses hardware counters and iteratively uses the XGBoost algorithm to build a performance model, ranks the importance of the microarchitecture events of the big data task, and reduces the performance big data dimension, so as to optimize the big data algorithm according to the performance characteristics described. Undoubtedly, the comprehensive monitoring of the sports training process is complex system engineering. The main monitoring includes three aspects: physical condition, technical and tactical skills, and intelligence. Sports technology is reflected in the ultimate load. According to the convenience and actual needs of the research, this article will discuss the methods of evaluating tennis training load and the actual technical and tactical parameter characteristics that can be obtained by studying the characteristics of tennis, namely, kinematics. Parameters for noncontact testing, the next step is to discuss the appropriateness and necessity of the load, as well as the technical and routine monitoring of tennis training ability. The final experimental results show that it can improve the physical energy of tennis players by more than 17%.

Cache filtering algorithm for least frequently used data with accurate memory simulation

We propose a cache filtering algorithm to improve processor performance using a small buffer inside the processor and an algorithm to filter least frequently used accesses from Ll and L2 caches. The algorithm uses simple DRAM fast-page accessing mode to identity accesses that are not previously accessed or not frequently used and keep them out of the cache system and store them in small buffer. We have also added a realistic page interleaved DDR3 memory simulation model to the SimpleScalar simulator. This model supports any processor and memory clock speeds, different sets of memory latencies, various configurations of memory banks and channels. Results show that the filtering algorithm could improve· performance of some applications compared to the same system that does not use the filtering algorithm

Cache filtering algorithm for least frequently used data with accurate memory simulation

We propose a cache filtering algorithm to improve processor performance using a small buffer inside the processor and an algorithm to filter least frequently used accesses from Ll and L2 caches. The algorithm uses simple DRAM fast-page accessing mode to identity accesses that are not previously accessed or not frequently used and keep them out of the cache system and store them in small buffer. We have also added a realistic page interleaved DDR3 memory simulation model to the SimpleScalar simulator. This model supports any processor and memory clock speeds, different sets of memory latencies, various configurations of memory banks and channels. Results show that the filtering algorithm could improve· performance of some applications compared to the same system that does not use the filtering algorithm

Assessment of expected reliability of applied software for computer-based information systems

The reliability of computer-based information systems is largely determined by the reliability of the developed application software. The failure rate of its computer program is considered as an indicator of the reliability of the application software. To determine the expected reliability of the application software planned for the development (until writing the code of a program), the model is proposed that uses some parameters of the future computer program, data on the influence of various factors on its reliability, and further testing of the program. The model takes into account the field of software application and computer processor performance. The process of model parameters obtaining is analyzed., It is possible by use of proposed model to determine the predicted failure rate of the planned application computer program, and then the reliability of the computer-based information system as a whole. If necessary, the measures can be developed to ensure the required level of reliability of the computer-based information system.

Towards the Improving Branch Instructions Identification in High- Performance Processors: Issues, Challenges and Techniques

Introduction: Accurate branch prediction technique has become compulsory in the superscalar and deep pipeline processors. The conditional instructions can break the continuous flow of execution in the pipeline stages, thereby decreasing processor performance. Discussion: This paper highlights the concept of branch prediction, some issues and challenges, and techniques for improving processor performance. Further, this paper also presents the role of branch prediction in different processors and their features. Conclusion: The concept of the branch prediction used in parallel processors to enhance the execution speed of the conditional branch instructions and improve the processor's performance is highlighted in this paper. Further, this paper highlights the branch predictor techniques with their features and presents the challenges, issues, and future techniques related to the branch prediction.

Microprocessors KOMDIV for High Performance Embedded Systems

The problems of creating of high-performance embedded computing systems based on microprocessors KOMDIV is considered. Processor performance is dependent upon three characteristics: clock cycle, clock cycles per instruction, and instruction count. These characteristics for microprocessors KOMDIV are optimized using parameter performance/power consumption and requirements of embedded systems.