A simulation study on lot release control, mask scheduling, and batch scheduling in semiconductor wafer fabrication facilities

Journal of Manufacturing Systems ◽

10.1016/s0278-6125(98)80024-1 ◽

1998 ◽

Vol 17 (2) ◽

pp. 107-117 ◽

Author(s):

Kim Yeong-Dae ◽

Lee Dong-Ho ◽

Kim Jung-Ug ◽

Roh Hwan-Kyun

Keyword(s):

Simulation Study ◽

Batch Scheduling ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Release Control

Download Full-text

Dynamic Release Control Policy for the Semiconductor Wafer Fabrication Lines

Journal of the Operational Research Society ◽

10.1057/jors.1996.195 ◽

1996 ◽

Vol 47 (12) ◽

pp. 1516-1525 ◽

Author(s):

Jongsoo Kim ◽

Robert C. Leachman ◽

Byungkyoo Suh

Keyword(s):

Control Policy ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Release Control

Download Full-text

Simulation experimental investigation on job release control in semiconductor wafer fabrication

2007 Winter Simulation Conference ◽

10.1109/wsc.2007.4419797 ◽

2007 ◽

Author(s):

Chao Qi ◽

Appa Iyer Sivakumar ◽

Stanley B. Gershwin

Keyword(s):

Experimental Investigation ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Release Control

Download Full-text

Learning-based release control of semiconductor wafer fabrication facilities

2015 Winter Simulation Conference (WSC) ◽

10.1109/wsc.2015.7408400 ◽

2015 ◽

Author(s):

Li Li ◽

Zhongbo Chen ◽

Qingyun Yu ◽

Nan Xiang

Keyword(s):

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Release Control

Download Full-text

A new release control policy (WRELM) for semiconductor wafer fabrication facilities

Proceedings of the 11th IEEE International Conference on Networking, Sensing and Control ◽

10.1109/icnsc.2014.6819601 ◽

2014 ◽

Author(s):

Z.B. Chen ◽

X.W. Pan ◽

L. Li ◽

Q.J. Chen ◽

W.S Xu

Keyword(s):

Control Policy ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Release Control

Download Full-text

A simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication

Production Planning & Control ◽

10.1080/095372898233722 ◽

1998 ◽

Vol 9 (7) ◽

pp. 714-722 ◽

Author(s):

Yi-Feng Hung ◽

Ing-Ren Chen

Keyword(s):

Simulation Study ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

Download Full-text

Dynamic Release Control Policy for the Semiconductor Wafer Fabrication Lines

Journal of the Operational Research Society ◽

10.2307/3010609 ◽

1996 ◽

Vol 47 (12) ◽

pp. 1516

Author(s):

Jongsoo Kim ◽

Robert C. Leachman ◽

Byungkyoo Suh

Keyword(s):

Control Policy ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication ◽

Release Control

Download Full-text

A Simulation Study on Dispatching Rules in Semiconductor Wafer Fabrication Facilities with Due Date-based Objectives

2006 IEEE International Conference on Systems, Man and Cybernetics ◽

10.1109/icsmc.2006.385039 ◽

2006 ◽

Author(s):

Tsung-Che Chiang ◽

Li-Chen Fu

Keyword(s):

Simulation Study ◽

Wafer Fabrication ◽

Dispatching Rules ◽

Due Date ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

Download Full-text

A performance model of automated material handling systems with double closed-loops and shortcuts in 300 mm semiconductor wafer fabrication systems

Journal of Manufacturing Systems ◽

10.1016/j.jmsy.2020.12.006 ◽

2021 ◽

Vol 58 ◽

pp. 316-334

Author(s):

Lihui Wu ◽

Zhongwei Zhang ◽

Jie Zhang ◽

Ray Y. Zhong ◽

Junliang Wang

Keyword(s):

Material Handling ◽

Performance Model ◽

Wafer Fabrication ◽

Semiconductor Wafer ◽

Closed Loops ◽

Material Handling Systems ◽

Semiconductor Wafer Fabrication ◽

Automated Material Handling ◽

Automated Material Handling Systems ◽

Download Full-text

Scheduling semiconductor wafer fabrication

IEEE Transactions on Semiconductor Manufacturing ◽

10.1109/66.4384 ◽

1988 ◽

Vol 1 (3) ◽

pp. 115-130 ◽

Author(s):

L.M. Wein

Keyword(s):

Wafer Fabrication ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

Download Full-text

AN ANALYSIS OF DISPATCHING RULES IN A SEMICONDUCTOR WAFER FABRICATION ENVIRONMENT

Journal of Electronics Manufacturing ◽

10.1142/s0960313195000190 ◽

1995 ◽

Vol 05 (03) ◽

pp. 165-174 ◽

Author(s):

THOMAS McCUTCHEN ◽

CHUNG-YEE LEE

Keyword(s):

Wafer Fabrication ◽

Dispatching Rules ◽

Semiconductor Wafer ◽

Semiconductor Wafer Fabrication

Download Full-text