Ranking Routes In Semiconductor Wafer Fabs

We develop a method to estimate the quality of processing routes in a wafer fabrication process. Ranking such routes can be useful for identifying the “best” and “worst” routes when making adjustments to recipes. Route categorization is also useful in developing efficient scheduling algorithms. In particular, we propose a method for ranking routes based on count-based metrics such as the number of defects on a wafer. We start with a statistical model to produce a “local” ranking of a tool and then build a “global” ranking via a heuristic procedure. Creating a fully statistical procedure for ranking routes in semiconductor fabrication plants is virtually impossible, given the number of possible routes and the limited data available. Nonetheless, our discussions with working engineers indicate that even approximate rankings are useful for making better operational decisions.

Tracking and Synchronization with Inversion-Based ILC for a Multi-Actuator-Driven Wafer Inspection Cartridge Transport Robot System

This paper proposes a simple tracking and synchronization control of a dual-drive system using inversion-based iterative learning control (IILC), which reformulates the model at each iteration based on input/output data. By the power of the IILC, this work simplifies the dual-actuator-driven dynamic system control problem that is normally addressed with a MIMO method. This work also shows the potential of the IILC for nonlinear system applications by reformulating the model at each iteration based on the input/output data. An analytical representation of the iteration-varying IILC followed by simulations is provided. A set of physical system testings with a dual-motor gantry and a semiconductor wafer inspection robotic system are carried out to verify the control method.

Wafer fusion technique features for near-IR laser sources

The paper presents the results of studies of the conditions for the formation of A3B5 compound semiconductors heterointerfaces including InP, InGaAsP and GaAs layers. The heterostructures were grown by molecular-beam epitaxy and were fused by wafer fusion technique. Improvement of planarity and homogeneity over the thickness of heterointerface due to using optimized preliminary preparation of semiconductor wafer surfaces was demonstrated. No additional extended defects such as dislocations were found.

Creative Approaches for Thermal Hot Spot Identification on Analog IC

With the increase in the complexity of semiconductor wafer fabrication processes, the timing in responding and discovering the failure mechanism to a product failure at the initial product development stage or at the end of production line becomes a crucial factor. Effectively utilization the fault localization technique such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) may be significantly shortened the cycle time in the fault localization process. This paper will illustrate the creative approaches for thermal hot spot identification using modulated THS technique coupled with modified external electrical connection.

DEPOSITION OF Al/SnAl OHMIC CONTACT ON SILICON FROM A LIQUID PHASE

Background. Single- and multi-layer metal films are widely utilized in modern electronics and optoelectronics as ohmic contacts. As a rule, the films are deposited by thermal evaporation, ion sputtering and chemical vapour deposition. However the methods of deposition from a liquid phase are the most simple and cost-effective. Thus the ohmic contact deposition by these methods is still an actual problem. Objective. The purpose of the paper is to study the possibility of deposition of multi-layer ohmic metal films over a semiconductor wafer surface from a liquid phase, particularly by scanning liquid phase epitaxy technique. Methods. In this work we considered the influence of a long-term temperature gradient at the interface metallic solution-melt – semiconductor wafer on the possibility of deposition of multi-layer ohmic metal films on the semiconductor wafer surface during segmental contact between the solution-melt and the wafer. For this purpose we carried out the simulation of heat transport process, wafer wetting process as well as the process of wafer cleansing off the solution-melt taking into account capillary phenomena in the mask openings using the method of scanning liquid phase epitaxy. For experimental confirmation of adequacy of the model proposed we carried out the deposition of Al/SnAl layer on silicon wafer in the above mentioned conditions. Results. We have deposited the contact layer Al/SnAl on the surface of silicon wafer from Al-Sn solution-melt by scanning liquid phase epitaxy technique using supplementary heater for the wafer and mask installed in the apparatus. The contact layer is made as three identical pads located at different distance one from each other. By the analysis of current-voltage characteristic we determined that the metallic film contact with the semiconductor is a non-rectifying, i.e. ohmic contact. The specific contact resistance was determined by the Transmission Line Method using linear configuration of the contact pads (LTLM). Its value was 7.2∙10-4 Ohm·cm2. Conclusions. The principal possibility of obtaining of multi-layer ohmic contacts to the semiconductor by scanning liquid phase epitaxy technique in conditions of segmental contact between the solution-melt and the wafer as well as long-term gradient at the contact interface was shown. The conditions were realized by using extra heating of the wafer back side and the high-temperature mask through which the solution-melt contacted the wafer.