Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )

A scalable systolic array architecture for the 2D discrete wavelet transform

38th Midwest Symposium on Circuits and Systems. Proceedings ◽

10.1109/mwscas.1995.510290 ◽

2002 ◽

Author(s):

Jijun Chen ◽

M.A. Bayoumi

Keyword(s):

Wavelet Transform ◽

Discrete Wavelet Transform ◽

Systolic Array ◽

Discrete Wavelet ◽

Array Architecture

A systolic array architecture for the Applebaum-Howells array

IEEE Transactions on Antennas and Propagation ◽

10.1109/8.56974 ◽

1990 ◽

Vol 38 (8) ◽

pp. 1310-1313 ◽

Cited By ~ 3

Author(s):

M. Ueno ◽

K. Kawabata ◽

T. Morooka

Keyword(s):

Systolic Array ◽

Array Architecture

A 2 1/2 -dimensional systolic array architecture

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 ◽

10.1109/iscas.1994.409242 ◽

2002 ◽

Author(s):

S.P.S. Lam

Keyword(s):

Systolic Array ◽

Array Architecture

Systolic-array architecture for 2D IIR Wideband dual-beam space-time plane-wave filters

2010 53rd IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2010.5548677 ◽

2010 ◽

Cited By ~ 2

Author(s):

Chamith Wijenayake ◽

Arjuna Madanayake ◽

Len T. Bruton

Keyword(s):

Plane Wave ◽

Systolic Array ◽

Space Time ◽

Dual Beam ◽

Array Architecture ◽

Wave Filters

A systolic array architecture for image coding using vector quantization

10.1109/vtsa.1989.68628 ◽

2003 ◽

Cited By ~ 2

Author(s):

S. Panchanathan ◽

M. Goldberg

Keyword(s):

Vector Quantization ◽

Systolic Array ◽

Image Coding ◽

Array Architecture

Compact FPGA-based systolic array architecture suitable for vision systems

Fourth International Conference on Information Technology (ITNG'07) ◽

10.1109/itng.2007.209 ◽

2007 ◽

Cited By ~ 1

Author(s):

Griselda Saldana ◽

Miguel Arias-Estrada

Keyword(s):

Systolic Array ◽

Vision Systems ◽

Array Architecture

A fast parallel implementation of the Berlekamp-Massey algorithm with a 1D systolic array architecture

Applied Algebra, Algebraic Algorithms and Error-Correcting Codes - Lecture Notes in Computer Science ◽

10.1007/3-540-60114-7_32 ◽

1995 ◽

pp. 415-426 ◽

Cited By ~ 6

Author(s):

Shojiro Sakata ◽

Masazumi Kurihara

Keyword(s):

Systolic Array ◽

Parallel Implementation ◽

Array Architecture

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.4.559 ◽

2005 ◽

Vol E88-C (4) ◽

pp. 559-569 ◽

Cited By ~ 14

Author(s):

J. MIYAKOSHI

Keyword(s):

Motion Estimation ◽

Low Power ◽

Systolic Array ◽

Block Matching ◽

Array Architecture

Automatic Interior I/O Elimination in Systolic Array Architecture

2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) ◽

10.1109/fccm.2018.00062 ◽

2018 ◽

Author(s):

Jason Cong ◽

Jie Wang

Keyword(s):

Systolic Array ◽

Array Architecture

2-D Systolic Array architecture of CBNS based Discrete Hilbert Transform Processor

Microprocessors and Microsystems ◽

10.1016/j.micpro.2020.103509 ◽

2020 ◽

pp. 103509

Author(s):

Madhumita Mukherjee ◽

Salil Kumar Sanyal

Keyword(s):

Hilbert Transform ◽

Systolic Array ◽

Discrete Hilbert Transform ◽

Array Architecture