High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis

A.H. Namin; K. Leboeuf; R. Muscedere; H. Wu; M. Ahmadi

doi:10.1049/iet-cds.2008.0331

High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2008.0331 ◽

2010 ◽

Vol 4 (2) ◽

pp. 168 ◽

Cited By ~ 3

Author(s):

A.H. Namin ◽

K. Leboeuf ◽

R. Muscedere ◽

H. Wu ◽

M. Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Hardware Implementation ◽

Normal Basis ◽

Finite Field Multiplier

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A high speed word level finite field multiplier using reordered normal basis

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4542158 ◽

2008 ◽

Cited By ~ 5

Author(s):

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Normal Basis ◽

Word Level ◽

Finite Field Multiplier

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High Speed Word-parallel Bit-Serial Normal Basis Finite Field Multiplier and Its FPGA Implementation

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005. ◽

10.1109/acssc.2005.1599981 ◽

2006 ◽

Cited By ~ 2

Author(s):

A.H. Namin ◽

Huapeng Wu ◽

M. Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Fpga Implementation ◽

Normal Basis ◽

Finite Field Multiplier ◽

Bit Serial

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Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2018.2851958 ◽

2018 ◽

Vol 26 (11) ◽

pp. 2542-2552

Author(s):

Parham Hosseinzadeh Namin ◽

Crystal Roma ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Vlsi Implementation ◽

Domino Logic ◽

Finite Field Multiplier

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Low power design of a word-level finite field multiplier using Reordered Normal Basis

2015 49th Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2015.7421165 ◽

2015 ◽

Author(s):

Parham Hosseinzadeh Namin ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Low Power ◽

Low Power Design ◽

Normal Basis ◽

Word Level ◽

Finite Field Multiplier

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Efficient VLSI implementation of a finite field multiplier using reordered normal basis

2010 53rd IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2010.5548774 ◽

2010 ◽

Cited By ~ 1

Author(s):

Karl Leboeuf ◽

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Vlsi Implementation ◽

Finite Field Multiplier

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A High-Speed Word Level Finite Field Multiplier in ${\BBF}_{2^m}$ Using Redundant Representation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2003005 ◽

2009 ◽

Vol 17 (10) ◽

pp. 1546-1550 ◽

Cited By ~ 6

Author(s):

A.H. Namin ◽

Huapeng Wu ◽

M. Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Word Level ◽

Finite Field Multiplier ◽

Redundant Representation

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High-speed hardware implementation of Gaussian normal basis inversion algorithm overF2m

Microelectronics Journal ◽

10.1016/j.mejo.2017.04.001 ◽

2017 ◽

Vol 63 ◽

pp. 138-147 ◽

Cited By ~ 4

Author(s):

Bahram Rashidi

Keyword(s):

High Speed ◽

Hardware Implementation ◽

Normal Basis ◽

Inversion Algorithm ◽

Gaussian Normal Basis

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Corrections to ``An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation''

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3114580 ◽

2021 ◽

pp. 1-1

Author(s):

Moslem Heidarpur ◽

Mitra Mirhassani

Keyword(s):

Finite Field ◽

High Speed ◽

Fpga Implementation ◽

Finite Field Multiplier

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An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3058509 ◽

2021 ◽

pp. 1-10

Author(s):

Moslem Heidarpur ◽

Mitra Mirhassani

Keyword(s):

Finite Field ◽

High Speed ◽

Finite Field Multiplier

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A Word-Level Finite Field Multiplier Using Normal Basis

IEEE Transactions on Computers ◽

10.1109/tc.2010.235 ◽

2011 ◽

Vol 60 (6) ◽

pp. 890-895 ◽

Cited By ~ 16

Author(s):

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Word Level ◽

Finite Field Multiplier

Download Full-text