An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation

2021 ◽  
pp. 1-10
Author(s):  
Moslem Heidarpur ◽  
Mitra Mirhassani
Keyword(s):  
Finite Field ◽  
High Speed ◽  
Finite Field Multiplier

scholarly journals Design of High Speed and Area Efficient Finite Field Multiplier Using Factoring Technique for Communication

2021 ◽  
Vol 2089 (1) ◽  
pp. 012071
Author(s):  
S Baba Fariddin ◽  
Rahul Mishra
Keyword(s):  
Finite Field ◽  
Data Security ◽  
High Speed ◽  
Input Data ◽  
Present Generation ◽  
Finite Field Multiplier ◽  
Simulation Results ◽  
Area Efficient

Abstract In this paper, design of high speed and area efficient finite field multiplier using factoring technique for communication is implemented. Data security plays very important role in present generation. Therefore, initially inputs and key are given to S-Box. The main intent of S-Box is to substitute the input data and key. After that input data and key are merged using S-Box merge. This data will be multiplied using finite field multiplier and to improve the performance along with that mix column technique is applied. Factoring technique will increase the speed of operation. After the data performs shift row operation. At last rounding is performed to the obtained data. At last simulation results shows that effective outcome in terms of delay, memory and security.

High speed VLSI implementation of a finite field multiplier using redundant representation

2009 ◽  
Author(s):  
Ashkan Hosseinzadeh Namin ◽  
Karl Leboeuf ◽  
Roberto Muscedere ◽  
Huapeng Wu ◽  
Majid Ahmadi
Keyword(s):  
Finite Field ◽  
High Speed ◽  
Vlsi Implementation ◽  
Finite Field Multiplier ◽  
Redundant Representation
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