Low-complexity low-memory energy-efficient image coding for wireless image sensor networks

2017 ◽  
Vol 66 (2) ◽  
pp. 125-132 ◽  
Author(s):  
G. Suseela ◽  
Y. Asnath Victy Phamila
Keyword(s):  
Sensor Networks ◽  
Image Coding ◽  
Energy Efficient ◽  
Low Complexity ◽  
Image Sensor

Low Complexity DCT Approximation for Image Compression in Wireless Image Sensor Networks

2016 ◽  
Vol 25 (08) ◽  
pp. 1650088 ◽  
Author(s):  
Khaoula Mechouek ◽  
Nasreddine Kouadria ◽  
Noureddine Doghmane ◽  
Nadia Kaddeche
Keyword(s):  
Energy Consumption ◽  
Sensor Networks ◽  
Low Complexity ◽  
Image Sensor ◽  
Experimental Comparison ◽  
Approximation Techniques ◽  
Dct Approximation ◽  
Dct Transformation ◽  
Computationally Intensive ◽  
Save Energy

Energy consumption is a critical problem affecting the lifetime of wireless image sensor networks (WISNs). In such systems, images are usually compressed using JPEG standard to save energy during transmission. And since DCT transformation is the most computationally intensive part in the JPEG technique, several approximation techniques have been proposed to further decrease the energy consumption. In this paper, we propose a low-complexity DCT approximation method which is based on the combination of the rounded DCT with a pruned approach. Experimental comparison with recently proposed schemes, using Atmel Atmega128L platform, shows that our method requires less arithmetic operations, and hence less processing time and/or the energy consumption while providing better performance in terms of PSNR metric.

Low Complexity Processor Designs for Energy-Efficient Security and Error Correction in Wireless Sensor Networks

2012 ◽  
pp. 348-366 ◽  
Author(s):  
J. H. Kong ◽  
J. J. Ong ◽  
L.-M. Ang ◽  
K. P. Seng
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Error Correction ◽  
Energy Efficient ◽  
Small Area ◽  
Low Complexity ◽  
Wireless Sensor ◽  
Battery Life ◽  
Processor Designs ◽  
Hardware Designs

This chapter presents low complexity processor designs for energy-efficient security and error correction for implementation on wireless sensor networks (WSN). WSN nodes have limited resources in terms of hardware, memory, and battery life span. Small area hardware designs for encryption and error-correction modules are the most preferred approach to meet the stringent design area requirement. This chapter describes Minimal Instruction Set Computer (MISC) processor designs with a compact architecture and simple hardware components. The MISC is able to make use of a small area of the FPGA and provides a processor platform for security and error correction operations. In this chapter, two example applications, which are the Advance Encryption Standard (AES) and Reed Solomon (RS) algorithms, were implemented onto MISC. The MISC hardware architecture for AES and RS were designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.

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