scholarly journals A Discrete Wavelet Transform (DWT)-Based Energy-Efficient Selective Retransmission Mechanism for Wireless Image Sensor Networks

2012 ◽  
Vol 1 (1) ◽  
pp. 3-35 ◽  
Author(s):  
Daniel G. Costa ◽  
Luiz Affonso Guedes
Keyword(s):  
Wavelet Transform ◽  
Sensor Networks ◽  
Discrete Wavelet Transform ◽  
Energy Efficient ◽  
Image Sensor ◽  
Discrete Wavelet ◽  
Retransmission Mechanism

scholarly journals Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform

2019 ◽  
Vol 7 (3) ◽  
pp. 197
Author(s):  
Khamees Khalaf Hasan ◽  
Ibrahim Khalil Salih ◽  
Abdumuttalib. A. Hussen
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Energy Efficient ◽  
Lifting Scheme ◽  
Building Design ◽  
Discrete Wavelet ◽  
Quartus Ii ◽  
Speed Performance ◽  
Level Building ◽  
Vhdl Code

<span lang="EN-US">This paper presents low power Discrete Wavelet Transform DWT architecture, comprising of forward and inverse multilevel transform for 5/3 lifting scheme LS based wavelet transform filter. This LS filter consists of integer adder units and binary shifter rather than multiplier and divider units as in the convolution based filters; hence it is more adaptable to energy efficient hardware performance. The proposed architecture is described using the VHDL based methodology. This VHDL code has been simulated and synthesized to achieve the gate level building design which can be organized to be effectively developed in hardware environment. The Quartus II 9.1 software synthesis tools were employed to implement 2D-DWT VHDL codes in Altera Development board DE2, with Cyclone II FPGA device. The proposed LS wavelet architectures can be attained by focusing on the physical FPGA devices to considerably decrease the needed hardware expenditure and power consumption of the design. The utilized logic and register elements of the architecture are 127 slices (only 1%) usage from 33216 and the architecture consumes only 0.033 W. Simulations were performed using different sizes of gray scale images that authenticate the proposed design and attain a speed performance appropriate for numerous real-time applications.</span>

FPGA Implementation of a High-Speed Two Dimensional Discrete Wavelet Transform

2013 ◽  
Vol 479-480 ◽  
pp. 508-512
Author(s):  
Chin Fa Hsieh ◽  
Tsung Han Tsai
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Real Time ◽  
High Speed ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Image Sensor ◽  
Discrete Wavelet ◽  
Two Dimensional ◽  
Clock Period

This paper proposes high-speed VLSI architecture for implementing a forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme is used to increase the clock rate, which allows its critical path to take only one adder delay. The proposed design enables 100% hardware use and faster computing than other 2D DWT architecture. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array (FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.

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