Energy consumption and performance comparison of DE optimization and PSO based IP core mapping technique for 2-D and 3-D network-on-chip

Author(s):  
Jayshree ◽  
Gopalakrishnan Seetharaman ◽  
Debadatta Pati
2014 ◽  
Vol 539 ◽  
pp. 296-302
Author(s):  
Dong Li

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.


2011 ◽  
Vol 8 (13) ◽  
pp. 986-993 ◽  
Author(s):  
Youhui Zhang ◽  
Xiaoguo Dong ◽  
Siqing Gan ◽  
Weimin Zheng

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