ScienceGate
Advanced Search
Author Search
Journal Finder
Blog
Sign in / Sign up
ScienceGate
Search
Author Search
Journal Finder
Blog
Sign in / Sign up
Interconnect testing using BIST embedded in IEEE 1149.1 designs
[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit
◽
10.1109/asic.1991.242914
◽
2002
◽
Cited By ~ 6
Author(s):
J. Koeter
◽
S. Sparks
Keyword(s):
Interconnect Testing
◽
Ieee 1149.1
Download Full-text
Related Documents
Cited By
References
A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD
Proceedings Eighth Asian Test Symposium (ATS'99)
◽
10.1109/ats.1999.810735
◽
2003
◽
Cited By ~ 2
Author(s):
W. Feng
◽
W.K. Huang
◽
F.J. Meyer
◽
F. Lombardi
Keyword(s):
Interconnect Testing
◽
Ieee 1149.1
Download Full-text
Development of Cloud Service for Interconnect Testing on HEMS Devices
IEEJ Transactions on Electronics Information and Systems
◽
10.1541/ieejeiss.133.818
◽
2013
◽
Vol 133
(4)
◽
pp. 818-819
Author(s):
Hiroshi Sugimura
◽
Kazuo Sekiya
◽
Tomoki Watanabe
◽
Masao Isshiki
Keyword(s):
Cloud Service
◽
Interconnect Testing
Download Full-text
A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port
Microprocessing and Microprogramming
◽
10.1016/0165-6074(92)90359-f
◽
1992
◽
Vol 35
(1-5)
◽
pp. 493-500
Author(s):
Mark Royals
◽
Tassos Markas
◽
Nick Kanopoulos
Keyword(s):
Boundary Scan
◽
Standard Interface
◽
Ieee 1149.1
Download Full-text
Toshiba IEEE 1149.1 (JTAG) development summary
[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit
◽
10.1109/asic.1991.242915
◽
2002
◽
Author(s):
J. Thomas
Keyword(s):
Ieee 1149.1
Download Full-text
Interconnect Testing for Networks on Chips
24th IEEE VLSI Test Symposium
◽
10.1109/vts.2006.41
◽
2006
◽
Cited By ~ 25
Author(s):
K. Stewart
◽
S. Tragoudas
Keyword(s):
Interconnect Testing
◽
Networks On Chips
Download Full-text
FPGA test time reduction through a novel interconnect testing scheme
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02
◽
10.1145/503048.503069
◽
2002
◽
Cited By ~ 8
Author(s):
Stuart McCracken
◽
Zeljko Zilic
Keyword(s):
Test Time
◽
Interconnect Testing
◽
Testing Scheme
◽
Test Time Reduction
◽
Time Reduction
Download Full-text
Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals
Proceedings ETC 93 Third European Test Conference
◽
10.1109/etc.1993.246575
◽
2002
◽
Cited By ~ 2
Author(s):
J. Andrews
Keyword(s):
Ieee 1149.1
Download Full-text
Adapting jtag for ac interconnect testing
International Test Conference, 2003. Proceedings. ITC 2003.
◽
10.1109/test.2003.1270892
◽
2004
◽
Cited By ~ 2
Author(s):
L. Whetsel
Keyword(s):
Interconnect Testing
Download Full-text
Core interconnect testing hazards
Proceedings Design, Automation and Test in Europe
◽
10.1109/date.1998.655985
◽
2002
◽
Author(s):
P. Nordholz
◽
H. Grabinski
◽
D. Treytnar
◽
J. Otterstedt
◽
D. Niggemeyer
◽
...
Keyword(s):
Interconnect Testing
Download Full-text
An implementation of IEEE 1149.1 to avoid timing violations and other practical in-compliance improvements
Proceedings. International Test Conference
◽
10.1109/test.2002.1041827
◽
2003
◽
Cited By ~ 1
Author(s):
D. Stang
◽
R. Dandapani
Keyword(s):
Ieee 1149.1
◽
Timing Violations
Download Full-text
Sign in / Sign up
Close
Export Citation Format
Close
Share Document
Close