Automated debugging of counterexamples in formal verification of pipelined microprocessors

17th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2012.6165044 ◽

2012 ◽

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Formal Verification ◽

Automated Debugging ◽

Pipelined Microprocessors

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Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors

Formal Methods and Software Engineering - Lecture Notes in Computer Science ◽

10.1007/978-3-642-16901-4_24 ◽

2010 ◽

pp. 355-370 ◽

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Formal Verification ◽

Error Tolerance ◽

Tolerance Mechanisms ◽

Pipelined Microprocessors

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Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) ◽

10.1109/dac.1999.781348 ◽

2003 ◽

Author(s):

M.N. Velev ◽

R.E. Bryant

Keyword(s):

Formal Verification ◽

Pipelined Microprocessors

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Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors

Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99 ◽

10.1145/309847.309967 ◽

1999 ◽

Author(s):

Miroslav N. Velev ◽

Randal E. Bryant

Keyword(s):

Formal Verification ◽

Pipelined Microprocessors

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Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for Boolean encoding of cardinality

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2014.7001425 ◽

2014 ◽

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Symmetry Breaking ◽

Automated Debugging ◽

Pipelined Microprocessors

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Automatic formal verification of multithreaded pipelined microprocessors

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2011.6105403 ◽

2011 ◽

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Formal Verification ◽

Pipelined Microprocessors

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A scalable formal verification methodology for pipelined microprocessors

33rd Design Automation Conference Proceedings, 1996 ◽

10.1145/240518.240624 ◽

1996 ◽

Author(s):

Jeremy Levitt ◽

Kunle Olukotun

Keyword(s):

Formal Verification ◽

Verification Methodology ◽

Pipelined Microprocessors

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A scalable formal verification methodology for pipelined microprocessors

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545638 ◽

2005 ◽

Author(s):

J. Levitt ◽

K. Olukotun

Keyword(s):

Formal Verification ◽

Verification Methodology ◽

Pipelined Microprocessors

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FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation

Model Checking Software - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31759-0_17 ◽

2012 ◽

pp. 234-240 ◽

Author(s):

Heinz Riener ◽

Görschwin Fey

Keyword(s):

Formal Verification ◽

Test Generation ◽

Software Test ◽

Automated Debugging

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Formal Verification of Pipelined Microprocessors with Delayed Branches

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.68 ◽

2006 ◽

Author(s):

M.N. Velev

Keyword(s):

Formal Verification ◽

Pipelined Microprocessors

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Formal Verification of Analysis Approach for Enterprise Information Systems Architecture Using Hypergraph Representation Based on Finite State Machines for Supporting Business Process Requirements

Journal of Applied Business and Economics ◽

10.33423/jabe.v22i9.3686 ◽

2020 ◽

Vol 22 (9) ◽

Keyword(s):

Information Systems ◽

Formal Verification ◽

Business Process ◽

Analysis Approach ◽

State Machines ◽

Enterprise Information ◽

Systems Architecture ◽

Enterprise Information Systems ◽

Finite State ◽

Information Systems Architecture

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