Introducing GOP-level quantization parameter offset in high efficiency video coding

2016 ◽  
Author(s):  
L. Xu ◽  
C. Zhu ◽  
Y. Zhou ◽  
Y. Wang ◽  
Y. Gao
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Quantization Parameter ◽  
High Efficiency Video Coding ◽  
Level Quantization

scholarly journals High Efficiency Video Coding Compliant Perceptual Video Coding Using Entropy Based Visual Saliency Model

Entropy ◽  
2019 ◽  
Vol 21 (10) ◽  
pp. 964 ◽  
Author(s):  
Muhammad Zeeshan ◽  
Muhammad Majid
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Visual Saliency ◽  
Quantization Parameter ◽  
High Efficiency Video Coding ◽  
Saliency Model ◽  
Salient Regions ◽  
Perceptual Video Coding ◽  
Visual Saliency Model ◽  
Visual Saliency Models

In past years, several visual saliency algorithms have been proposed to extract salient regions from multimedia content in view of practical applications. Entropy is one of the important measures to extract salient regions, as these regions have high randomness and attract more visual attention. In the context of perceptual video coding (PVC), computational visual saliency models that utilize the charactertistics of the human visual system to improve the compression ratio are of paramount importance. To date, only a few PVC schemes have been reported that use the visual saliency model. In this paper, we conduct the first attempt to utilize entropy based visual saliency models within the high efficiency video coding (HEVC) framework. The visual saliency map generated for each input video frame is optimally thresholded to generate a binary saliency mask. The proposed HEVC compliant PVC scheme adjusts the quantization parameter according to visual saliency relevance at the coding tree unit (CTU) level. Efficient CTU level rate control is achieved by allocating bits to salient and non-salient CTUs by adjusting the quantization parameter values according to their perceptual weighted map. The attention based on information maximization has shown the best performance on newly created ground truth dataset, which is then incorporated in a HEVC framework. An average bitrate reduction of 6 . 57 % is achieved by the proposed HEVC compliant PVC scheme with the same perceptual quality and a nominal increase in coding complexity of 3 . 34 % when compared with HEVC reference software. Moreover, the proposed PVC scheme performs better than other HEVC based PVC schemes when encoded at low data rates.

High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder

2016 ◽  
Vol 11 (9) ◽  
pp. 764
Author(s):  
Lella Aicha Ayadi ◽  
Nihel Neji ◽  
Hassen Loukil ◽  
Mouhamed Ali Ben Ayed ◽  
Nouri Masmoudi
Keyword(s):  
Video Coding ◽  
High Performance ◽  
High Efficiency ◽  
High Efficiency Video Coding

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

2021 ◽  
Vol 49 (4) ◽  
pp. 1013-1027
Author(s):  
Hajar Touzani ◽  
Anass Mansouri ◽  
Fatima Errahimi ◽  
Ali Ahaitouf
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
High Efficiency Video Coding
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