GF(q) LDPC decoder design for FPGA implementation

2013 IEEE 10th Consumer Communications and Networking Conference (CCNC) ◽

10.1109/ccnc.2013.6488484 ◽

2013 ◽

Author(s):

W. Sulek ◽

M. Kucharczyk ◽

G. Dziwoki

Keyword(s):

Fpga Implementation ◽

Ldpc Decoder ◽

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Non-binary LDPC Decoder Design over Rayleigh Channel for FPGA Implementation

TELKOMNIKA (Telecommunication Computing Electronics and Control) ◽

10.12928/telkomnika.v14i4.4157 ◽

2016 ◽

Vol 14 (4) ◽

pp. 1376

Author(s):

Zhongxun Wang ◽

Juan Hui

Keyword(s):

Fpga Implementation ◽

Ldpc Decoder ◽

Rayleigh Channel ◽

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FPGA Implementation of LDPC Decoder Architecture for Wireless Communication Standards

2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST) ◽

10.1109/mocast52088.2021.9493380 ◽

2021 ◽

Author(s):

Ruslan Goriushkin ◽

Pavel Nikishkin ◽

Evgeny Likhobabin ◽

Vladimir Vityaze

Keyword(s):

Wireless Communication ◽

Fpga Implementation ◽

Ldpc Decoder ◽

Decoder Architecture

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Error Resilience and Energy Efficiency: An LDPC Decoder Design Study

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0023 ◽

2016 ◽

Author(s):

Philipp Schläfer ◽

Chu-Hsiang Huang ◽

Clayton Schoeny ◽

Christian Weis ◽

Yao Li ◽

...

Keyword(s):

Energy Efficiency ◽

Error Resilience ◽

Design Study ◽

Ldpc Decoder ◽

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FPGA implementation of LDPC decoder for 5G NR with parallel layered architecture and adaptive normalization

2020 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech) ◽

10.1109/eexpolytech50912.2020.9243997 ◽

2020 ◽

Author(s):

Alexandr Katyushnyj ◽

Aleksei Krylov ◽

Andrey Rashich ◽

Chao Zhang ◽

Kewu Peng

Keyword(s):

Fpga Implementation ◽

Ldpc Decoder ◽

Layered Architecture

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Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms

IEICE Transactions on Electronics ◽

10.1093/ietele/e90-c.10.1964 ◽

2007 ◽

Vol E90-C (10) ◽

pp. 1964-1971

Author(s):

Q. WANG ◽

K. SHIMIZU ◽

T. IKENAGA ◽

S. GOTO

Keyword(s):

Ldpc Decoder ◽

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A bit-serial approximate min-sum LDPC decoder and FPGA implementation

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1692544 ◽

2006 ◽

Author(s):

A. Darabiha ◽

A.C. Carusone ◽

F.R. Kschischang

Keyword(s):

Fpga Implementation ◽

Ldpc Decoder ◽

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An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2010.2042255 ◽

2010 ◽

Vol 45 (4) ◽

pp. 843-855 ◽

Author(s):

Zhengya Zhang ◽

Venkat Anantharam ◽

Martin J. Wainwright ◽

Borivoje Nikolic

Keyword(s):

Ldpc Decoder ◽

Decoder Design ◽

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FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

Journal of Networks ◽

10.4304/jnw.6.1.36-45 ◽

2011 ◽

Vol 6 (1) ◽

Author(s):

Vikram Arkalgud Chandrasetty ◽

Syed Mahfuzul Aziz

Keyword(s):

Message Passing ◽

Fpga Implementation ◽

Ldpc Decoder ◽

Message Passing Algorithm ◽

Reduced Complexity

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A solution for memory collision in semi-parallel FPGA-based LDPC decoder design

2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2007.4487366 ◽

2007 ◽

Author(s):

Radivoje Zarubica ◽

Stephen G. Wilson

Keyword(s):

Ldpc Decoder ◽

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FPGA implementation of a clockless stochastic LDPC decoder

2014 IEEE Workshop on Signal Processing Systems (SiPS) ◽

10.1109/sips.2014.6986088 ◽

2014 ◽

Author(s):

Chris Ceroici ◽

Vincent C. Gaudet

Keyword(s):

Fpga Implementation ◽

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